INFORMATION ADVANCE
TMS320C6678 |
|
|
||
Multicore Fixed and Floating-Point Digital Signal Processor |
||||
SPRS691—November 2010 |
|
www.ti.com |
||
|
|
|
|
|
Table 3-18 |
Timer Output Selection Field Description (TOUTPSEL) (Part 2 of 2) |
|||
|
|
|
|
|
Bit |
Field |
|
Description |
|
4 |
Reserved |
Reserved |
|
|
|
|
|
|
|
4-0 |
TOUTPSEL0 |
Output select for TIMO0 |
|
|
|
|
|
00000: TOUTL0 |
10000: TOUTL8 |
|
|
|
00001: TOUTH0 |
10001: TOUTH8 |
|
|
|
00010: TOUTL1 |
10010: TOUTL9 |
|
|
|
00011: TOUTH1 |
10011: TOUTH9 |
|
|
|
00100: TOUTL2 |
10100: TOUTL10 |
|
|
|
00101: TOUTH2 |
10101: TOUTH10 |
|
|
|
00110: TOUTL3 |
10110: TOUTL11 |
|
|
|
00111: TOUTH3 |
10111: TOUTH11 |
|
|
|
01000: TOUTL4 |
11000: TOUTL12 |
|
|
|
01001: TOUTH4 |
11001: TOUTH12 |
|
|
|
01010: TOUTL5 |
11010: TOUTL13 |
|
|
|
01011: TOUTH5 |
11011: TOUTH13 |
|
|
|
01100: TOUTL6 |
11100: TOUTL14 |
|
|
|
01101: TOUTH6 |
11101: TOUTH14 |
|
|
|
01110: TOUTL7 |
11110: TOUTL15 |
|
|
|
01111: TOUTH7 |
11111: TOUTH15 |
|
|
|
|
|
End of Table 3-18 |
|
|
||
|
|
|
|
|
3.3.18 Reset Mux (RSTMUXx) Register
The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through RSTMUX7 for each of the eight CorePacs on the C6678. These registers are located in Bootcfg memory space. The Timer Output Selection Register is shown in Figure 3-17 and described in Table 3-19.
Figure 3-17 Reset Mux Register RSTMUXx
31 |
10 |
9 |
8 |
7 |
5 |
4 |
3 |
1 |
0 |
|
|
|
|
|
|
|
|
|
|
|
Reserved |
EVTSTATCLR |
Reserved |
|
DELAY |
EVTSTAT |
|
OMODE |
LOCK |
|
|
|
|
|
|
|
|||
R, +0000 0000 0000 0000 0000 00 |
RC, +0 |
R, +0 |
RW, +100 |
R, +0 |
RW, +000 |
RW, +0 |
|||
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear |
|
|
|
|
|||||
Table 3-19 |
Reset Mux Register Field Descriptions (Part 1 of 2) |
|||
|
|
|
|
|
Bit |
Field |
|
Description |
|
31-10 |
Reserved |
Reserved |
||
|
|
|
||
9 |
EVTSTATCLR |
0 = Writing O had no effect |
||
|
|
|
1 = Writing 1 to this bit clears the EVTSTAT bit |
|
|
|
|
||
8 |
Reserved |
Reserved |
||
|
|
|
|
|
7-5 |
DELAY |
|
000b = 256 DSP/6 cycles delay between NMI & Local reset, when OMODE = 100b |
|
|
|
|
001b |
= 512 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b |
|
|
|
010b |
= 1024 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b |
|
|
|
011b |
= 2048 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b |
|
|
|
100b |
= 4096 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b (Default) |
|
|
|
101b |
= 8192 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b |
|
|
|
110b |
= 16384 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b |
|
|
|
111b |
= 32768 DSP/6 cycles delay between NMI & Local reset, when OMODE=100b |
|
|
|
||
4 |
EVTSTAT |
0 = No event received (Default) |
||
|
|
|
1 = WD timer event received by Reset Mux block |
|
|
|
|
|
|
78 |
Device Configuration |
Copyright 2010 Texas Instruments Incorporated |
|
|
|
|
TMS320C6678 |
|
|
|
|
Multicore Fixed and Floating-Point Digital Signal Processor |
www.ti.com |
|
|
SPRS691—November 2010 |
|
|
|
|
||
Table 3-19 |
Reset Mux Register Field Descriptions (Part 2 of 2) |
|||
|
|
|
|
|
Bit |
Field |
|
Description |
|
3-1 |
OMODE |
|
000b = WD Timer Event input to the Reset Mux block does not cause any output event (Default) |
|
|
|
|
001b |
= Reserved |
|
|
|
010b |
= WD Timer Event input to the Reset Mux block causes local reset input to CorePac |
|
|
|
011b |
= WD Timer Event input to the Reset Mux block causes NMI input to CorePac |
|
|
|
100b |
= WD Timer Event input to the Reset Mux block causes NMI input followed by Local reset input to CorePac. Delay |
|
|
|
between NMI and local reset is set in DELAY bit field. |
|
|
|
|
101b |
= WD Timer Event input to the Reset Mux block causes Device Reset to C6678 |
|
|
|
110b |
= Reserved |
|
|
|
111b |
= Reserved |
|
|
|
|
|
0 |
LOCK |
|
0 = Register fields are not locked (Default) |
|
|
|
|
1 = Register fields are locked until the next timer reset |
|
|
|
|
|
|
End of Table 3-19 |
|
|||
|
|
|
|
|
ADVANCE INFORMATION
Copyright 2010 Texas Instruments Incorporated |
Device Configuration |
79 |