INFORMATION ADVANCE

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

5.1 Memory Architecture

Each C66x CorePac of the TMS320C6678 device contains a 512KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The device also contain a 4096KB multicore shared memory (MSM). All memory on the C6678 has a unique location in the memory map (see Table 2-2 ‘‘Memory Map Summary for TMS320C6678’’ on page 19.

The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PCFG) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.

The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the Bootloader for the C66x DSP User Guide (literature number SPRUGY5).

For more information on the operation L1 and L2 caches, see the C66x DSP Cache User Guide (literature number SPRUGY8).

5.1.1 L1P Memory

The L1P memory configuration for the C6678 device is as follows:

•Region 0 size is 0K bytes (disabled)

•Region 1 size is 32K bytes with no wait states

Figure 5-2 shows the available SRAM/cache configurations for L1P.

Figure 5-2 TMS320C6678 L1P Memory Configurations

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

5.1.2 L1D Memory

The L1D memory configuration for the C6678 device is as follows:

•Region 0 size is 0K bytes (disabled)

•Region 1 size is 32K bytes with no wait states

Figure 5-3 shows the available SRAM/cache configurations for L1D.

Figure 5-3 TMS320C6678 L1D Memory Configurations

5.1.3 L2 Memory

The L2 memory configuration for the C6678 device is as follows:

•Total memory size is 4096KB

•Each core contains 512KB of memory

•Local starting address for each core is 0080 0000h

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INFORMATION ADVANCE

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C66x CorePac. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset.

Figure 5-4 TMS320C6678 L2 Memory Configurations

Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to zero. The aliasing is handled within the C66x CorePac and allows for common code to be run unmodified on multiple cores. For example, address location 0x10800000 is the global base address for C66x CorePac Core 0's L2 memory. C66x CorePac Core 0 can access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the cores as their own L2 base addresses.

For C66x CorePac Core 0, as mentioned, this is equivalent to 0x10800000, for C66x CorePac Core 1 this is equivalent to 0x11800000, and for C66x CorePac Core 2 this is equivalent to 0x12800000. Local addresses should be used only for shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run-time by a particular core should always use the global address only.

5.1.4 MSMC SRAM

The MSMC SRAM configuration for the C6678 device is as follows:

•Memory size is 4096KB

•The MSMC SRAM can be configured as shared L2 and/or shared L3 memory

•Allows extension of external addresses from 2GB to up to 8GB

•Has built in memory protection features