INFORMATION ADVANCE

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

7.7 Reset Controller

The reset controller detects the different type of resets supported on the TMS320C6678 device and manages the distribution of those resets throughout the device.

The device has several types of resets:

•Power-on reset

•Hard reset

•Soft reset

•CPU local reset

Table 7-59 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more information on the effects of each reset on the PLL controllers and their clocks, see Section ‘‘Reset Electrical Data / Timing’’ on page 211

7.7.1 Power-on Reset

Power-on reset is used to reset the entire device, including the test and emulation logic.

Power-on reset is initiated by the following

1.POR pin

2.RESETFULL pin

During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. A RESETFULL pin is also provided to allow the on-board host to reset the entire device including the reset isolated logic. The assumption is that, device is already powered up and hence unlike POR, RESETFULL pin will be driven by the on-board host control other than the power good circuitry. For power-on reset, the Main PLL controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the state of the PLL or the dividers in the PLL controller.

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

The following sequence must be followed during a power-on reset:

1.Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and will remain at their reset state until otherwise configured by their respective peripheral. All peripherals that are power managed, are disabled after a Power-on Reset and must be enabled through the Device State Control registers (for more details, see Section Table 3-2 ‘‘Device State Control Registers’’ on page 62).

2.Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in reset.

3.POR must be held active until all supplies on the board are stable then for at least an additional time for the Chip level PLLs to lock.

4.The POR pin can now be de-asserted. Reset sampled pin values are latched at this point. The Chip level PLLs is taken out of reset and begins its locking sequence, and all power-on device initialization also begins.

5.After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, DDR3 PLL has already completed its locking sequence and is outputting a valid clock. The system clocks of both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks. After the pause, the system clocks are restarted at their default divide by settings.

6.The device is now out of reset and device execution begins as dictated by the selected boot mode.

Note—To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period of the POR pin, most of the device will remain in reset. The RESET pin should not be tied together with the POR pin.

7.7.2 Hard Reset

A Hard reset will reset everything on the device except the PLLs, test, emulation logic and reset isolation modules.

POR should also remain de-asserted during this time.

Hard reset is initiated by the following

•RESET pin

•RSCTRL register in PLLCTL

•Watchdog Timer

•Emulation

All the above initiators by default are configured to act as Hard reset. Except Emulation all the other 3 initiators can be configured as Soft resets in the RSCFG register in PLLCTL.

The following sequence must be followed during a Hard reset:

1.The RESET pin is pulled active low for a minimum of 24 CLKIN1 cycles. During this time the RESET signal is able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules affected by RESET, to prevent off-chip contention during the warm reset.

2.Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.

3.The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration pins are not re-latched and clocking is unaffected within the device.

4.After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).

Note—The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied together with the POR pin.

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TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

7.7.3 Soft Reset

A soft reset will behave like a hard reset except that the PCIe MMRs and DDR3 EMIF MMRs contents are retained. POR should also remain de-asserted during this time.

Soft reset is initiated by the following

•RESET pin

•RSCTRL register in PLLCTL

•Watchdog Timer

•Emulation

All the above initiators by default are configured to act as Hard reset. Except Emulation all the other 3 initiators can be configured as Soft resets in the RSCFG register in PLLCTL.

In the case of a soft reset, the clock logic or the power control logic of the peripherals are not affected, and, therefore, the enabled/disabled state of the peripherals is not affected. The following external memory contents are maintained during a soft reset:

•DDR3 MMRs: The DDR3 Memory Controller registers are not reset. In addition, the DDR3 SDRAM memory content is retained if the user places the DDR3 SDRAM in self-refresh mode before invoking the soft reset.

•PCIe MMRs: The contents of the memory connected to the EMIFA are retained. The EMIFA registers are not reset.

During a soft reset, the following happens:

1.The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate through the system. Internal system clocks are not affected. PLLs also remain locked.

2.After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL controllers pause their system clocks for about 8 cycles.

At this point:

›The state of the peripherals before the soft reset is not changed.

›The I/O pins are controlled as dictated by the DEVSTAT register.

›The DDR3 MMRs and PCIe MMRs retain their previous values. Only the DDR3 Memory Controller and PCIe state machines are reset by the soft reset.

›The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.

The boot sequence is started after the system clocks are restarted. Since the configuration pins are not latched with a System Reset, the previous values, as shown in the DEVSTAT register, are used to select the boot mode.

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

7.7.4 Local Reset

The local reset can be used to reset a particular CorePac without resetting any other chip components.

Local reset is initiated by the following (for more details see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide (literature number SPRUGV2):

•LRESET pin

•Watchdog Timer should cause one of the below based on Reset Multiplex “ESTMUXn” register setting (See TBD for details):

–Local Reset

–NMI

–NMI followed by a time delay and then a local reset for the core selected

–Hard Reset by requesting reset via PLLCTL

•LPSC MMRs

7.7.5 Reset Priority

If any of the above reset sources occur simultaneously, the PLLCTL processes only the highest priority reset request. The reset request priorities are as follows (high to low):

•Power-on reset

•Hard/Soft reset

7.7.6 Reset Controller Register

The reset controller register are part of the PLLCTL MMRs. All C6678 device-specific MMRs are covered in Section 7.8.4 ‘‘Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing’’ on page 224. For more details on these registers and how to program them, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide (literature number SPRUGV2).

7.7.7 Reset Electrical Data / Timing

Table 7-60 Reset Timing Requirements (1)

(see Figure 7-18, Figure 7-19, Figure 7-20 and Figure 7-21)

End of Table 7-60

Copyright 2010 Texas Instruments Incorporated TMS320C6678 Peripheral Information and Electrical Specifications 211

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INFORMATION ADVANCE

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

1 C = 1 ÷ CORECLK(N|P) frequency in ns.

Figure 7-18 Power-On Reset Timing

1

2

VDDS15 Stable + Clocks Valid (internal signal)

POR

RESET

RESETFULL

3

RESETSTAT

Figure 7-19 Full-Reset Timing

4 5

6

RESETFULL

RESET

7

RESETSTAT

POR

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

Figure 7-20 Hard-Reset Timing

8 9

10

RESET

RESETFULL

11

RESETSTAT

POR

Figure 7-21 Soft-Reset Timing

1 C = 1 ÷ CORECLK(N|P) frequency in ns.

Figure 7-22 Boot Configuration Timing

1

POR

GPIO[15:0]/

DONE

2

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