- •Data Manual
- •Release History
- •Contents
- •List of Figures
- •List of Tables
- •1 Features
- •1.1 KeyStone Architecture
- •1.2 Device Description
- •1.3 Functional Block Diagram
- •2 Device Overview
- •2.1 Device Characteristics
- •2.2 DSP Core Description
- •2.3 Memory Map Summary
- •2.4 Boot Sequence
- •2.5 Boot Modes Supported and PLL Settings
- •2.5.1 Boot Device Field
- •2.5.2 Device Configuration Field
- •2.5.2.1 Sleep / EMIF16 Boot Device Configuration
- •2.5.2.2 Ethernet (SGMII) Boot Device Configuration
- •2.5.2.3 Serial Rapid I/O Boot Device Configuration
- •2.5.2.4 PCI Boot Device Configuration
- •2.5.2.5 I2C Boot Device Configuration
- •2.5.2.6 SPI Boot Device Configuration
- •2.5.2.7 HyperLink Boot Device Configuration
- •2.5.3 PLL Boot Configuration Settings
- •2.6 Second-Level Bootloaders
- •2.7 Terminals
- •2.8 Terminal Functions
- •2.9 Development
- •2.9.1 Development Support
- •2.9.2 Device Support
- •2.9.2.1 Device and Development-Support Tool Nomenclature
- •Related Documentation from Texas Instruments
- •3 Device Configuration
- •3.1 Device Configuration at Device Reset
- •3.2 Peripheral Selection After Device Reset
- •3.3 Device State Control Registers
- •3.3.1 Device Status Register
- •3.3.2 Device Configuration Register
- •3.3.3 JTAG ID (JTAGID) Register Description
- •3.3.4 Kicker Mechanism (KICK0 and KICK1) Register
- •3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
- •3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
- •3.3.7 Reset Status (RESET_STAT) Register
- •3.3.8 Reset Status Clear (RESET_STAT_CLR) Register
- •3.3.9 Boot Complete (BOOTCOMPLETE) Register
- •3.3.10 Power State Control (PWRSTATECTL) Register
- •3.3.11 NMI Even Generation to CorePac (NMIGRx) Register
- •3.3.12 IPC Generation (IPCGRx) Registers
- •3.3.13 IPC Acknowledgement (IPCARx) Registers
- •3.3.14 IPC Generation Host (IPCGRH) Register
- •3.3.15 IPC Acknowledgement Host (IPCARH) Register
- •3.3.16 Timer Input Selection Register (TINPSEL)
- •3.3.17 Timer Output Selection Register (TOUTPSEL)
- •3.3.18 Reset Mux (RSTMUXx) Register
- •3.4 Pullup/Pulldown Resistors
- •4 System Interconnect
- •4.1 Internal Buses, Bridges, and Switch Fabrics
- •4.2 Data Switch Fabric Connections
- •4.3 Configuration Switch Fabric
- •4.4 Bus Priorities
- •5 C66x CorePac
- •5.1 Memory Architecture
- •5.1.1 L1P Memory
- •5.1.2 L1D Memory
- •5.1.3 L2 Memory
- •5.1.4 MSMC SRAM
- •5.1.5 L3 Memory
- •5.2 Memory Protection
- •5.3 Bandwidth Management
- •5.4 Power-Down Control
- •5.5 C66x CorePac Resets
- •5.6 C66x CorePac Revision
- •5.7 C66x CorePac Register Descriptions
- •6 Device Operating Conditions
- •6.1 Absolute Maximum Ratings
- •6.2 Recommended Operating Conditions
- •6.3 Electrical Characteristics
- •7 TMS320C6678 Peripheral Information and Electrical Specifications
- •7.1 Parameter Information
- •7.1.1 1.8-V Signal Transition Levels
- •7.1.2 Timing Parameters and Board Routing Analysis
- •7.2 Recommended Clock and Control Signal Transition Behavior
- •7.3 Power Supplies
- •7.3.1 Power-Supply Sequencing
- •7.3.1.1 POR-Controlled Device Initialization
- •7.3.1.2 RESETFULL-Controlled Device Initialization
- •7.3.1.3 Prolonged Resets
- •7.3.2 Power-Down Sequence
- •7.3.3 Power Supply Decoupling and Bulk Capacitors
- •7.3.4 SmartReflex
- •7.4 Enhanced Direct Memory Access (EDMA3) Controller
- •7.4.1 EDMA3 Device-Specific Information
- •7.4.2 EDMA3 Channel Synchronization Events
- •7.4.3 EDMA3 Peripheral Register Description(s)
- •7.5 Interrupts
- •7.5.1 Interrupt Sources and Interrupt Controller
- •7.5.2 INTC Registers
- •7.5.2.1 INTC0/INTC1 Register Map
- •7.5.2.2 INTC2 Register Map
- •7.5.2.3 INTC3 Register Map
- •7.5.3 Inter-Processor Register Map
- •7.5.4 External Interrupts Electrical Data/Timing
- •7.6.1 MPU Registers
- •7.6.1.1 MPU Register Map
- •7.6.1.2 Device-Specific MPU Registers
- •7.6.2 MPU Programmable Range Registers
- •7.6.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
- •7.6.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
- •7.6.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
- •7.7 Reset Controller
- •7.7.1 Power-on Reset
- •7.7.2 Hard Reset
- •7.7.3 Soft Reset
- •7.7.4 Local Reset
- •7.7.5 Reset Priority
- •7.7.6 Reset Controller Register
- •7.7.7 Reset Electrical Data / Timing
- •7.8 Main PLL and PLL Controller
- •7.8.1 Main PLL Controller Device-Specific Information
- •7.8.1.1 Internal Clocks and Maximum Operating Frequencies
- •7.8.1.2 Main PLL Controller Operating Modes
- •7.8.1.3 Main PLL Stabilization, Lock, and Reset Times
- •7.8.2 PLL Controller Memory Map
- •7.8.2.1 PLL Secondary Control Register (SECCTL)
- •7.8.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
- •7.8.2.3 PLL Controller Clock Align Control Register (ALNCTL)
- •7.8.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
- •7.8.2.5 SYSCLK Status Register (SYSTAT)
- •7.8.2.6 Reset Type Status Register (RSTYPE)
- •7.8.2.7 Reset Control Register (RSTCTRL)
- •7.8.2.8 Reset Configuration Register (RSTCFG)
- •7.8.2.9 Reset Isolation Register (RSISO)
- •7.8.3 Main PLL Control Register
- •7.8.4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
- •7.9.1 DDR3 PLL Control Register
- •7.9.2 DDR3 PLL Device-Specific Information
- •7.9.3 DDR3 PLL Input Clock Electrical Data/Timing
- •7.10 PASS PLL
- •7.10.1 PASS PLL Control Register
- •7.10.2 PASS PLL Device-Specific Information
- •7.11 DDR3 Memory Controller
- •7.11.1 DDR3 Memory Controller Device-Specific Information
- •7.11.2 DDR3 Memory Controller Electrical Data/Timing
- •7.12 I2C Peripheral
- •7.12.1 I2C Device-Specific Information
- •7.12.2 I2C Peripheral Register Description(s)
- •7.12.3 I2C Electrical Data/Timing
- •7.12.3.1 Inter-Integrated Circuits (I2C) Timing
- •7.13 SPI Peripheral
- •7.13.1 SPI Electrical Data/Timing
- •7.13.1.1 SPI Timing
- •7.14 HyperLink Peripheral
- •7.15 UART Peripheral
- •7.16 PCIe Peripheral
- •7.17 TSIP Peripheral
- •7.18 EMIF16 Peripheral
- •7.19 Packet Accelerator
- •7.20 Security Accelerator
- •7.21 Ethernet MAC (EMAC)
- •7.22 Management Data Input/Output (MDIO)
- •7.23 Timers
- •7.23.1 Timers Device-Specific Information
- •7.23.2 Timers Electrical Data/Timing
- •7.24 Serial RapidIO (SRIO) Port
- •7.25 General-Purpose Input/Output (GPIO)
- •7.25.1 GPIO Device-Specific Information
- •7.25.2 GPIO Electrical Data/Timing
- •7.26 Semaphore2
- •7.27 Emulation Features and Capability
- •7.27.1 Advanced Event Triggering (AET)
- •7.27.2 Trace
- •7.27.2.1 Trace Electrical Data/Timing
- •7.27.3 IEEE 1149.1 JTAG
- •7.27.3.1 IEEE 1149.1 JTAG Compatibility Statement
- •7.27.3.2 JTAG Electrical Data/Timing
- •8 Mechanical Data
- •8.1 Thermal Data
- •8.2 Packaging Information
- •8.3 Package CYP
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TMS320C6678 |
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Multicore Fixed and Floating-Point Digital Signal Processor |
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www.ti.com |
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SPRS691—November 2010 |
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Table 7-68 |
PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions |
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Bit |
Field |
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Description |
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31-8 |
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6-5 |
Reserved |
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. |
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3-2 |
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0 |
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7 |
SYS8 |
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Identifies when the SYSCLKn divide ratio has been modified. |
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4 |
SYS5 |
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0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected. |
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1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio. |
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1 |
SYS2 |
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End of Table 7-68 |
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7.8.2.5 SYSCLK Status Register (SYSTAT)
The SYSCLK status register (SYSTAT) shows the status of SYSCLK[11:1]. SYSTAT is shown in Figure 7-28 and described in Table 7-69.
Figure 7-28 SYSCLK Status Register (SYSTAT)
31 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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Reserved |
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SYS11ON |
SYS10ON |
SYS9ON |
SYS8ON |
SYS7ON |
SYS6ON |
SYS5ON |
SYS4ON |
SYS3ON |
SYS2ON |
SYS1ON |
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R-n |
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R-1 |
R-1 |
R-1 |
R-1 |
R-1 |
R-1 |
R-1 |
R-1 |
R-1 |
R-1 |
R-1 |
Legend: R/W = Read/Write; R = Read only; -n = value after reset |
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Table 7-69 |
SYSCLK Status Register (SYSTAT) Field Descriptions |
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Bit |
Field |
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Description |
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31-11 |
Reserved |
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. |
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10-0 |
SYS[N (1)]ON |
SYSCLK[N] on status. |
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0 |
= SYSCLK[N] is gated. |
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1 |
= SYSCLK[N] is on. |
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End of Table 7-69 |
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1 Where N = 1, 2, 3,....N (Not all these output clocks may be used on a specific device. For more information, see the device-specific data manual)
7.8.2.6 Reset Type Status Register (RSTYPE)
The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The Reset Type Status register is shown in Figure 7-29 and described in Table 7-70.
Figure 7-29 Reset Type Status Register (RSTYPE)
31 |
29 |
28 |
27 |
12 |
11 |
8 |
7 |
3 |
2 |
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1 |
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0 |
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Reserved |
EMU-RST |
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Reserved |
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WDRST[N] |
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Reserved |
PLLCTRLRST |
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POR |
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RESET |
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R-0 |
R-0 |
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R-0 |
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R-0 |
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R-0 |
R-0 |
R-0 |
R-0 |
Legend: R = Read only; -n = value after reset
ADVANCE INFORMATION
Copyright 2010 Texas Instruments Incorporated |
TMS320C6678 Peripheral Information and Electrical Specifications 221 |
INFORMATION ADVANCE
TMS320C6678 |
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Multicore Fixed and Floating-Point Digital Signal Processor |
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SPRS691—November 2010 |
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www.ti.com |
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Table 7-70 |
Reset Type Status Register (RSTYPE) Field Descriptions |
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Field |
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Description |
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31-29 |
Reserved |
Reserved. Read only. Always reads as 0. Writes have no effect. |
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28 |
EMU-RST |
Reset initiated by emulation. |
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0 |
= Not the last reset to occur. |
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1 |
= The last reset to occur. |
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27-12 |
Reserved |
Reserved. Read only. Always reads as 0. Writes have no effect. |
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11 |
WDRST3 |
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Reset initiated by Watchdog Timer[N]. |
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10 |
WDRST2 |
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0 |
= Not the last reset to occur. |
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1 |
= The last reset to occur. |
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9 |
WDRST1 |
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8WDRST0
7-3 |
Reserved |
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Reserved. Read only. Always reads as 0. Writes have no effect. |
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2 |
PLLCTLRST |
Reset initiated by PLLCTL. |
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0 |
= Not the last reset to occur. |
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1 |
= The last reset to occur. |
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1 |
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reset. |
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RESET |
RESET |
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0 |
= |
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RESET |
was not the last reset to occur. |
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1 |
= |
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was the last reset to occur. |
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RESET |
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0 |
POR |
Power-on reset. |
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0 |
= Power-on reset was not the last reset to occur. |
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1 |
= Power-on reset was the last reset to occur. |
End of Table 7-70
7.8.2.7 Reset Control Register (RSTCTRL)
This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the RSTCTRL or the RSTCFG is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control register (RSTCTRL) is shown in Figure 7-30 and described in Table 7-71.
Figure 7-30 Reset Control Register (RSTCTRL)
31 |
17 |
16 |
15 |
0 |
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Reserved |
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SWRST |
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KEY |
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R-0x0000 |
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R/W-0x (1) |
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R/W-0x0003 |
Legend: R = Read only; -n = value after reset;
1 Writes are conditional based on valid key.
Table 7-71 Reset Control Register (RSTCTRL) Field Descriptions
Bit |
Field |
Description |
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31-17 |
Reserved |
Reserved. |
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16 |
SWRST |
Software reset |
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0 |
= Reset |
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1 |
= Not reset |
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15-0 |
KEY |
Key used to enable writes to RSTCTRL and RSTCFG. |
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End of Table 7-71 |
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222 TMS320C6678 Peripheral Information and Electrical Specifications |
Copyright 2010 Texas Instruments Incorporated |
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com |
SPRS691—November 2010 |
|
7.8.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset initiated by RESET, Watchdog Timer and the PLL controller’s RSTCTRL register; i.e., a Hard reset or a Soft reset. By default, these resets will be Hard resets. The Reset Configuration register (RSTCFG) is shown in Figure 7-31 and described in Table 7-72.
Figure 7-31 |
Reset Configuration Register (RSTCFG) |
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31 |
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16 |
15 |
14 |
13 |
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12 |
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11 |
4 |
3 |
0 |
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Reserved |
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Reserved |
PLLCTLRSTTYPE |
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Reserved |
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WDTYPE[N (1)] |
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RESETTYPE |
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R-0x0000 |
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R-00 |
R/W-0 (2) |
R/W-02 |
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R-0x0 |
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R/W-0x002 |
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Legend: R = Read only; R/W = Read/Write; -n = value after reset |
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1 |
Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data manual) |
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2 |
Writes are conditional based on valid key. For details, see Section 7.8.2.7 ‘‘Reset Control Register (RSTCTRL)’’. |
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Table 7-72 |
Reset Configuration Register (RSTCFG) Field Descriptions |
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Bit |
Acronym |
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Description |
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31-14 |
Reserved |
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Reserved. |
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13 |
PLLCTLRSTTYPE |
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PLL controller initiates a software-driven reset of type: |
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0 |
= Hard reset (default) |
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1 |
= Soft reset |
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12 |
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initiates a reset of type: |
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RESETTYPE |
RESET |
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0 |
= Hard Reset (default) |
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1 |
= Soft Reset |
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11-4 |
Reserved |
Reserved. |
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3 |
WDTYPE3 |
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Watchdog Timer [N] initiates a reset of type: |
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2 |
WDTYPE2 |
0 |
= Hard Reset (default) |
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1 |
= Soft Reset |
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1 |
WDTYPE1 |
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0WDTYPE0
End of Table 7-72
7.8.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through non Power-on reset. Setting any of these bits effectively blocks reset to all PLLCTL registers in order to maintain current values of PLL multiplier, divide ratios and other settings. The Reset Isolation register (RSTCTRL) is shown in Figure 7-32 and described in Table 7-73.
Figure 7-32 Reset Isolation Register (RSISO)
31 |
16 |
15 |
10 |
9 |
8 |
7 |
4 |
3 |
2 |
0 |
Reserved |
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Reserved |
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SRIOISO |
SRISO |
Reserved |
AIF2ISO |
Reserved |
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R-0x0000 |
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R-0x00 |
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R/W-0 |
R/W-0 |
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R-0x0 |
R/W-0 |
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R-000 |
Legend: R = Read only; R/W = Read/Write; -n = value after reset
ADVANCE INFORMATION
Copyright 2010 Texas Instruments Incorporated |
TMS320C6678 Peripheral Information and Electrical Specifications 223 |