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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / tms320c6678.pdf

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INFORMATION ADVANCE

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691—November 2010				www.ti.com
				www.ti.com
Table 7-73		Reset Isolation Register (RSISO) Field Descriptions

Bit	Acronym		Description
31-10	Reserved		Reserved.

9	SRIOISO		Isolate SRIO module
			0	= Not reset isolated
			1	= Reset Isolated

8	SRISO		Isolate SmartReflex
			0	= Not reset isolated
			1	= Reset Isolated

7-4	Reserved		Reserved.

3	AIF2ISO		Isolate AIF2 module
			0	= Not reset isolated
			1	= Reset isolated

2-0	Reserved		Reserved.

End of Table 7-73

7.8.3 Main PLL Control Register

The Main PLL uses a chip-level register (MAINPLLCTL) along with the PLL controller for its configuration. This MMR exists inside the Bootcfg space. To write to this register, software should go through an un-locking sequence using KICK0/KICK1 registers. For valid configurable values into the MAINPLLCTL register see Section 2.5.3 ‘‘PLL Boot Configuration Settings’’ on page 31. See section 3.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 66 for the address location of the registers and locking and unlocking sequences for accessing the registers. This register is reset on POR only.

Figure 7-33 Main PLL Control Register (MAINPLLCTL)

31	24	23	19	18	16	15	12	11	6	5	0

BWADJ[7:0]		Reserved			PLLM[12:6]			Reserved			PLLD

RW,+0000 0101		RW - 0000 0			RW,+0000000			RW, +000000		RW,+000000

Legend: RW = Read/Write; -n = value after reset

7.8.4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing

Table 7-74		Main PLL Control Register Field Descriptions

Bit	Field		Description
31-24	BWADJ[7:0]		BWADJ should be programmed to a value equal to half of PLLM[12:0]

23-19	Reserved		Reserved

18-12	PLLM[12:6]		A 13-bit bus that selects the values for the multiplication factor (see Note below)

11-6	Reserved		Reserved

5-0	PLLD		A 6-bit bus that selects the values for the reference divider

End of Table 7-74

Note—PLLM[5:0] bits of the multiplier is controlled by the PLLM register inside the PLL controller and PLLM[12:6] bits are controlled by the above chip level register. MAINPLLCTL register PLLM[12:6] bits should be written just before writing to PLLM register PLLM[5:0] bits in the controller to have the complete 13 bit value latched when the GO operation is initiated in the PLL controller. See the Phase Locked Loop

224 TMS320C6678 Peripheral Information and Electrical Specifications

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com	SPRS691—November 2010

(PLL) Controller for KeyStone Devices User Guide (literature number SPRUGV2) for the recommended programming sequence. Output Divide ratio and Bypass enable/disable of the Main PLL is controlled by the SECCTL register in the PLL Controller. See the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide (literature number SPRUGV2) for more details.

Table 7-75		Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (Part 1 of 2)
(see Figure 7-34 and Figure 7-35)

No.					Min	Max	Unit
			CORECLK[P:N]

1	tc(CORCLKN)		Cycle Time _ CORECLKN cycle time		10	25	ns

1	tc(CORECLKP)		Cycle Time _ CORECLKP cycle time		10	25	ns	INFORMATION

3	tw(CORECLKN)		Pulse Width _ CORECLKN high		0.45*tc(CORECLKN)	0.55*tc(CORECLKN)	ns
3	tw(CORECLKN)		Pulse Width _ CORECLKN high		0.45*tc(CORECLKN)	0.55*tc(CORECLKN)	ns

2	tw(CORECLKN)		Pulse Width _ CORECLKN low		0.45*tc(CORECLKN)	0.55*tc(CORECLKN)	ns

2	tw(CORECLKP)		Pulse Width _ CORECLKP high		0.45*tc(CORECLKP)	0.55*tc(CORECLKP)	ns

3	tw(CORECLKP)		Pulse Width _ CORECLKP low		0.45*tc(CORECLKP)	0.55*tc(CORECLKP)	ns

4	tr(CORECLKN_250mv)		Transition Time _ CORECLKN Rise time (250mV)		50	350	ps

4	tf(CORECLKN_250mv)		Transition Time _ CORECLKN Fall time (250mV)		50	350	ps

4	tr(CORECLKP_250mv)		Transition Time _ CORECLKP Rise time (250mV)		50	350	ps

4	tf(CORECLKP_250mv)		Transition Time _ CORECLKP Fall time (250mV)		50	350	ps

5	tj(CORECLKN)		Jitter, Peak_to_Peak _ Periodic CORECLKN			100	ps
								ADVANCE
5	tj(CORECLKP)		Jitter, Peak_to_Peak _ Periodic CORECLKP			100	ps

			SRIOSGMIICLK[P:N]

1	tc(SRIOSMGMIICLKN)		Cycle Time _ SRIOSMGMIICLKN cycle time		3.2	6.4	ns

1	tc(SRIOSMGMIICLKP)		Cycle Time _ SRIOSMGMIICLKP cycle time		3.2	6.4	ns

3	tw(SRIOSMGMIICLKN)		Pulse Width _ SRIOSMGMIICLKN high		0.45*tc(SRIOSGMIICLKN)	0.55*tc(SRIOSGMIICLKN)	ns

2	tw(SRIOSMGMIICLKN)		Pulse Width _ SRIOSMGMIICLKN low		0.45*tc(SRIOSGMIICLKN)	0.55*tc(SRIOSGMIICLKN)	ns

2	tw(SRIOSMGMIICLKP)		Pulse Width _ SRIOSMGMIICLKP high		0.45*tc(SRIOSGMIICLKP)	0.55*tc(SRIOSGMIICLKP)	ns

3	tw(SRIOSMGMIICLKP)		Pulse Width _ SRIOSMGMIICLKP low		0.45*tc(SRIOSGMIICLKP)	0.55*tc(SRIOSGMIICLKP)	ns

4	tr(SRIOSMGMIICLKN_25		Transition Time _ SRIOSMGMIICLKN Rise time (250mV)		50	350	ps
	0mv)				50	350	ps
	0mv)

4	tf(SRIOSMGMIICLKN_25		Transition Time _ SRIOSMGMIICLKN Fall time (250mV)		50	350	ps
	0mv)				50	350	ps
	0mv)

4	tr(SRIOSMGMIICLKP_25		Transition Time _ SRIOSMGMIICLKP Rise time (250mV)		50	350	ps
	0mv)				50	350	ps
	0mv)

4	tf(SRIOSMGMIICLKP_25		Transition Time _ SRIOSMGMIICLKP Fall time (250mV)		50	350	ps
	0mv)				50	350	ps
	0mv)

4	tr(SRIOSMGMIICLKN)		Transition Time _ SRIOSMGMIICLKN Rise time (VOH)		50	1300	ps

4	tf(SRIOSMGMIICLKP)		Transition Time _ SRIOSMGMIICLKN Fall time (VOH)		50	1300	ps

4	tr(SRIOSMGMIICLKN)		Transition Time _ SRIOSMGMIICLKP Rise time (VOH)		50	1300	ps

4	tf(SRIOSMGMIICLKP)		Transition Time _ SRIOSMGMIICLKP Fall time (VOH)		50	1300	ps

5	tj(SRIOSMGMIICLKN)		Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKN			4	ps,RMS

5	tj(SRIOSMGMIICLKP)		Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKP			4	ps,RMS

5	tj(SRIOSMGMIICLKN)		Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKN (SRIO			8	ps,RMS
			Not Used)			8	ps,RMS
			Not Used)

5	tj(SRIOSMGMIICLKP)		Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKP (SRIO			8	ps,RMS
			Not Used)			8	ps,RMS
			Not Used)

			MCMCLK[P:N]

1	tc(MCMCLKN)		Cycle Time _ MCMCLKN cycle time		3.2	6.4	ns

1	tc(MCMCLKP)		Cycle Time _ MCMCLKP cycle time		3.2	6.4	ns


Copyright 2010 Texas Instruments Incorporated				TMS320C6678 Peripheral Information and Electrical Specifications			225

	TMS320C6678
	Multicore Fixed and Floating-Point Digital Signal Processor
	SPRS691—November 2010					www.ti.com
						www.ti.com
	Table 7-75		Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (Part 2 of 2)
	(see Figure 7-34 and Figure 7-35)

	No.				Min	Max	Unit
	3	tw(MCMCLKN)		Pulse Width _ MCMCLKN high	0.45*tc(MCMCLKN)	0.55*tc(MCMCLKN)	ns

	2	tw(MCMCLKN)		Pulse Width _ MCMCLKN low	0.45*tc(MCMCLKN)	0.55*tc(MCMCLKN)	ns

	2	tw(MCMCLKP)		Pulse Width _ MCMCLKP high	0.45*tc(MCMCLKP)	0.55*tc(MCMCLKP)	ns

	3	tw(MCMCLKP)		Pulse Width _ MCMCLKP low	0.45*tc(MCMCLKP)	0.55*tc(MCMCLKP)	ns

	4	tr(MCMCLKN_250mv)		Transition Time _ MCMCLKN Rise time (250mV)	50	350	ps

	4	tf(MCMCLKN_250mv)		Transition Time _ MCMCLKN Fall time (250mV)	50	350	ps

ADVANCE	4	tr(MCMCLKP_250mv)		Transition Time _ MCMCLKP Rise time (250mV)	50	350	ps

	4	tf(MCMCLKP_250mv)		Transition Time _ MCMCLKP Fall time (250mV)	50	350	ps
	4	tf(MCMCLKP_250mv)		Transition Time _ MCMCLKP Fall time (250mV)	50	350	ps

	4	tr(MCMCLKN)		Transition Time _ MCMCLKN Rise time (VOH)	50	1300	ps

	4	tf(MCMCLKP)		Transition Time _ MCMCLKN Fall time (VOH)	50	1300	ps

	4	tr(MCMCLKN)		Transition Time _ MCMCLKP Rise time (VOH)	50	1300	ps

	4	tf(MCMCLKP)		Transition Time _ MCMCLKP Fall time (VOH)	50	1300	ps

	5	tj(MCMCLKN)		Jitter, Peak_to_Peak _ Periodic MCMCLKN		4	ps,RMS

INFORMATION	5	tj(MCMCLKP)		Jitter, Peak_to_Peak _ Periodic MCMCLKP		4	ps,RMS

				PCIECLK[P:N]
				PCIECLK[P:N]

	1	tc(PCIECLKN)		Cycle Time _ PCIECLKN cycle time	3.2	10	ns

	1	tc(PCIECLKP)		Cycle Time _ PCIECLKP cycle time	3.2	10	ns

	3	tw(PCIECLKN)		Pulse Width _ PCIECLKN high	0.45*tc(PCIECLKN)	0.55*tc(PCIECLKN)	ns

	2	tw(PCIECLKN)		Pulse Width _ PCIECLKN low	0.45*tc(PCIECLKN)	0.55*tc(PCIECLKN)	ns

	2	tw(PCIECLKP)		Pulse Width _ PCIECLKP high	0.45*tc(PCIECLKP)	0.55*tc(PCIECLKP)	ns

	3	tw(PCIECLKP)		Pulse Width _ PCIECLKP low	0.45*tc(PCIECLKP)	0.55*tc(PCIECLKP)	ns

	4	tr(PCIECLKN_250mv)		Transition Time _ PCIECLKN Rise time (250mV)	50	350	ps

	4	tf(PCIECLKN_250mv)		Transition Time _ PCIECLKN Fall time (250mV)	50	350	ps

	4	tr(PCIECLKP_250mv)		Transition Time _ PCIECLKP Rise time (250mV)	50	350	ps

	4	tf(PCIECLKP_250mv)		Transition Time _ PCIECLKP Fall time (250mV)	50	350	ps

	4	tr(PCIECLKN)		Transition Time _ PCIECLKN Rise time (VOH)	50	1300	ps

	4	tf(PCIECLKP)		Transition Time _ PCIECLKN Fall time (VOH)	50	1300	ps

	4	tr(PCIECLKN)		Transition Time _ PCIECLKP Rise time (VOH)	50	1300	ps

	4	tf(PCIECLKP)		Transition Time _ PCIECLKP Fall time (VOH)	50	1300	ps

	5	tj(PCIECLKN)		Jitter, Peak_to_Peak _ Periodic PCIECLKN		4	ps,RMS

	5	tj(PCIECLKP)		Jitter, Peak_to_Peak _ Periodic PCIECLKP		4	ps,RMS

	End of Table 7-75