TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com |
SPRS691—November 2010 |
|
5 C66x CorePac
The C66x CorePac consists of several components:
•The C66x DSP and associated C66x CorePac core
•Level-one and level-two memories (L1P, L1D, L2)
•Data Trace Formatter (DTF)
•Embedded Trace Buffer (ETB)
•Interrupt controller
•Power-down controller
•External memory controller
•Extended memory controller
•A dedicated power/sleep controller (LPSC)
The C66x CorePac also provides support for memory protection, bandwidth management (for resources local to the C66x CorePac) and address extension. Figure 5-1 shows a block diagram of the C66x CorePac.
Figure 5-1 C66x CorePac Block Diagram
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32KB L1P |
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Program Memory Controller (PMC) With |
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MemoryExtendedMemoryUnified |
(XMC)ControllerController(UMC) |
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Memory Protect/Bandwidth Mgmt |
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L2 Cache/ |
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GPSC |
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.M1 |
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.M2 |
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ControllerExceptionandInterrupt |
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SRAM |
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C66x DSP Core |
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512KB |
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Instruction Fetch |
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16-/32-bit Instruction Dispatch |
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Control Registers |
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MSM |
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In-Circuit Emulation |
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Boot |
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SRAM |
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Instruction Decode |
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Controller |
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4096KB |
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Data Path A |
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Data Path B |
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B Register File |
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DDR3 |
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A Register File |
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SRAM |
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PLLC |
LPSC |
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A31-A16 |
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B31-B16 |
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A15-A0 |
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B15-B0 |
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DMA Switch |
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.L1 |
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.S1 |
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.D1 |
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.D2 |
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.S2 |
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.L2 |
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Fabric |
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Memory |
(EMC) |
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External |
Controller |
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Memory Protect/Bandwidth Mgmt |
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Data Memory Controller (DMC) With |
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CFG Switch |
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Fabric |
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32KB L1D
For more detailed information on the TMS320C66x CorePac on the C6678 device, see the C66x CorePac User Guide (literature number SPRUGW0).
Copyright 2010 Texas Instruments Incorporated |
C66x CorePac |
85 |
ADVANCE INFORMATION