TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

The MSM SRAM is always configured as all SRAM. When configured as a shared L2, its contents can be cached in L1P and L1D. When configured in shared L3 mode, it’s contents can be cached in L2 also. For more details on external memory address extension and memory protection features, see the Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide (literature number SPRUGW7).

5.1.5 L3 Memory

The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement to block accesses from this portion to the ROM.

5.2 Memory Protection

Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (16KB each). The L1D, L1P, and L2 memory controllers in the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.

Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses. On a secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access.

The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify whether memory pages are locally or globally accessible.

The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection scheme, see Table 5-1.

Faults are handled by software in an interrupt (or an exception, programmable within the C66x CorePac interrupt controller) service routine. A DSP or DMA access to a page without the proper permissions will:

•Block the access — reads return zero, writes are ignored

•Capture the initiator in a status register — ID, address, and access type are stored

•Signal event to DSP interrupt controller

The software is responsible for taking corrective action to respond to the event and resetting the error status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User Guide (literature number SPRUGW0).

ADVANCE INFORMATION

INFORMATION ADVANCE

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

5.3 Bandwidth Management

When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to the highest priority requestor. The following four resources are managed by the Bandwidth Management control hardware:

•Level 1 Program (L1P) SRAM/Cache

•Level 1 Data (L1D) SRAM/Cache

•Level 2 (L2) SRAM/Cache

•Memory-mapped registers configuration bus

The priority level for operations initiated within the C66x CorePac are declared through registers in the C66x CorePac. These operations are:

•DSP-initiated transfers

•User-programmed cache coherency operations

•IDMA-initiated transfers

The priority level for operations initiated outside the C66x CorePac by system peripherals is declared through the Priority Allocation Register (PRI_ALLOC) System peripherals with no fields in PRI_ALLOC have their own registers to program their priorities, see section 4.4 ‘‘Bus Priorities’’ on page 84 for more details.

More information on the bandwidth management features of the C66x CorePac can be found in the C66x CorePac User Guide (literature number SPRUGW0.)

5.4 Power-Down Control

The C66x CorePac supports the ability to power-down various parts of the C66x CorePac. The power-down controller (PDC) of the C66x CorePac can be used to power down L1P, the cache control hardware, the DSP, and the entire C66x CorePac. These power-down features can be used to design systems for lower overall system power requirements.

Note—The C6678 does not support power-down modes for the L2 memory at this time.

More information on the power-down features of the C66x CorePac can be found in the TMS320C66x CorePac Reference Guide (literature number SPRUGW0).

5.5 C66x CorePac Resets

Table 5-2 shows the reset types supported on the C6678 device and how they affect the resetting of the CorePac, either both globally or just locally.

Table 5-2 C66x CorePac Reset (Global or Local)

For more detailed information on the global and local C66x CorePac resets, see the C66x CorePac Reference Guide (literature number SPRUGW0). And for more detailed information on device resets, see section 7.7 ‘‘Reset Controller’’ .

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

5.6 C66x CorePac Revision

The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Table 5-3 and described in Table 5-4. The C66x CorePac revision is dependant on the silicon revision being used.

5.7 C66x CorePac Register Descriptions

See the C66x CorePac Reference Guide (literature number SPRUGW0) for register offsets and definitions.

ADVANCE INFORMATION