INFORMATION ADVANCE
TMS320C6678 |
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Multicore Fixed and Floating-Point Digital Signal Processor |
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SPRS691—November 2010 |
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www.ti.com |
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Table 3-5 |
JTAG ID Register Field Descriptions |
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Bit |
Acronym |
Value |
Description |
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31-28 |
VARIANT |
0000b |
Variant (4-Bit) value. The value of this field depends on the silicon revision being used. |
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27-12 |
PART NUMBER |
0000 0000 1001 1110b |
Part Number for boundary scan |
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11-1 |
MANUFACTURER |
0000 0010 111b |
Manufacturer |
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0 |
LSB |
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1b |
This bit is read as a 1 for TMS320C6678 |
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End of Table 3-5 |
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3.3.4 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg MMR values. When the kicker is locked (which it is initially after power on reset) none of the Bootcfg MMRs are writable (they are only readable). This mechanism requires two MMR writes to the KICK0 and KICK1 registers with exact data values before the kicker lock mechanism is un-locked. See Table 3-2 ‘‘Device State Control Registers’’ on page 62 for the address location. Once released then all the Bootcfg MMRs having “write” permissions are writable (the read only MMRs are still read only). The first KICK0 data is 0x83e70b13. The second KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs will lock the kicker mechanism and block any writes to Bootcfg MMRs. In order to ensure protection to all Bootcfg MMRs, software must always re-lock the kicker mechanism after completing the MMR writes.
3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on CORESEL. The LRESETNMI PIN Status Register is shown in Figure 3-4 and described in Table 3-6.
Figure 3-4 LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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Reserved |
NMI7 |
NMI6 |
NMI5 |
NMI4 |
NMI3 |
NMI2 |
NMI1 |
NMI0 |
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Reserved |
LR7 |
LR6 |
LR5 |
LR4 |
LR3 |
LR2 |
LR1 |
LR0 |
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R, +0000 0000 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R, +0000 0000 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
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Legend: R = Read only; -n = value after reset |
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Table 3-6 |
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions (Part 1 of 2) |
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Bit |
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Field |
Description |
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31-24 |
Reserved |
Reserved |
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23 |
NMI7 |
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CorePac 7 in NMI |
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22 |
NMI6 |
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CorePac 6 in NMI |
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21 |
NMI5 |
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CorePac 5 in NMI |
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20 |
NMI4 |
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CorePac 4 in NMI |
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19 |
NMI3 |
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CorePac 3 in NMI |
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18 |
NMI2 |
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CorePac 2 in NMI |
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17 |
NMI1 |
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CorePac 1 in NMI |
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16 |
NMI0 |
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CorePac 0 in NMI |
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15-8 |
Reserved |
Reserved |
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7 |
LR7 |
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CorePac 7 in Local Reset |
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6 |
LR6 |
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CorePac 6 in Local Reset |
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5 |
LR5 |
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CorePac 5 in Local Reset |
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4 |
LR4 |
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CorePac 4 in Local Reset |
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66 Device Configuration |
Copyright 2010 Texas Instruments Incorporated |
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TMS320C6678 |
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Multicore Fixed and Floating-Point Digital Signal Processor |
www.ti.com |
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SPRS691—November 2010 |
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Table 3-6 |
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions (Part 2 of 2) |
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Bit |
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Field |
Description |
3 |
LR3 |
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CorePac 3 in Local Reset |
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2 |
LR2 |
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CorePac 2 in Local Reset |
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1 |
LR1 |
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CorePac 1 in Local Reset |
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0 |
LR0 |
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CorePac 0 in Local Reset |
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End of Table 3-6 |
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3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on CORESEL. The LRESETNMI PIN Status Clear Register is shown in Figure 3-5 and described in Table 3-7.
Figure 3-5 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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Reserved |
NMI7 |
NMI6 |
NMI5 |
NMI4 |
NMI3 |
NMI2 |
NMI1 |
NMI0 |
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Reserved |
LR7 |
LR6 |
LR5 |
LR4 |
LR3 |
LR2 |
LR1 |
LR0 |
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R, +0000 0000 |
WC,+ |
WC,+ |
WC,+ |
WC,+ |
WC,+ |
WC,+ |
WC,+ |
WC,+ |
R, +0000 0000 |
WC, |
WC, |
WC, |
WC, |
WC, |
WC, |
WC, |
WC, |
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0 (1) |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
1 RC: Write one to clear.
Table 3-7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions
Bit |
Field |
Description |
31-24 |
Reserved |
Reserved |
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23 |
NMI7 |
CorePac 7 in NMI Clear |
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22 |
NMI6 |
CorePac 6 in NMI Clear |
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21 |
NMI5 |
CorePac 5 in NMI Clear |
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20 |
NMI4 |
CorePac 4 in NMI Clear |
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19 |
NMI3 |
CorePac 3 in NMI Clear |
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18 |
NMI2 |
CorePac 2 in NMI Clear |
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17 |
NMI1 |
CorePac 1 in NMI Clear |
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16 |
NMI0 |
CorePac 0 in NMI Clear |
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15-8 |
Reserved |
Reserved |
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7 |
LR7 |
CorePac 7 in Local Reset Clear |
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6 |
LR6 |
CorePac 6 in Local Reset Clear |
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5 |
LR5 |
CorePac 5 in Local Reset Clear |
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4 |
LR4 |
CorePac 4 in Local Reset Clear |
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3 |
LR3 |
CorePac 3 in Local Reset Clear |
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2 |
LR2 |
CorePac 2 in Local Reset Clear |
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1 |
LR1 |
CorePac 1 in Local Reset Clear |
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0 |
LR0 |
CorePac 0 in Local Reset Clear |
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End of Table 3-7
ADVANCE INFORMATION
Copyright 2010 Texas Instruments Incorporated |
Device Configuration |
67 |
INFORMATION ADVANCE
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691—November 2010 |
www.ti.com |
|
3.3.7 Reset Status (RESET_STAT) Register
The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the global device reset (GR). Software can use this information to take different device initialization steps, if desired.
•In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives an local reset without receiving a global reset.
•In case of Global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is asserted.
The Reset Status Register is shown in Figure 3-6 and described in Table 3-8.
Figure 3-6 Reset Status Register (RESET_STAT)
31 |
30 |
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8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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GR |
Reserved |
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LR7 |
LR6 |
LR5 |
LR4 |
LR3 |
LR2 |
LR1 |
LR0 |
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R, +1 |
R, + 000 0000 0000 0000 |
0000 0000 |
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R,+0 |
R,+0 |
R,+0 |
R,+0 |
R,+0 |
R,+0 |
R,+0 |
R,+0 |
Legend: R = Read only; -n = value after reset |
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Table 3-8 |
Reset Status Register (RESET_STAT) Field Descriptions |
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Bit |
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Field |
Description |
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31 |
GR |
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Global reset status |
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0 |
= Device has not received a global reset. |
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1 |
= Device received a global reset. |
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30-8 |
Reserved |
Reserved. |
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7 |
LR7 |
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CorePac 7 reset status |
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0 |
= CorePac 7 has not received a local reset. |
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1 |
= CorePac 7 received a local reset. |
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6 |
LR6 |
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CorePac 6 reset status |
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0 |
= CorePac 6 has not received a local reset. |
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1 |
= CorePac 6 received a local reset. |
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5 |
LR5 |
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CorePac 5 reset status |
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0 |
= CorePac 5 has not received a local reset. |
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1 |
= CorePac 5 received a local reset. |
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4 |
LR4 |
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CorePac 4 reset status |
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0 |
= CorePac 4 has not received a local reset. |
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1 |
= CorePac 4 received a local reset. |
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3 |
LR3 |
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CorePac 3 reset status |
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0 |
= CorePac 3 has not received a local reset. |
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1 |
= CorePac 3 received a local reset. |
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2 |
LR2 |
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CorePac 2 reset status |
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0 |
= CorePac 2 has not received a local reset. |
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1 |
= CorePac 2 received a local reset. |
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1 |
LR1 |
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CorePac 1 reset status |
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0 |
= CorePac 1 has not received a local reset. |
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1 |
= CorePac 1 received a local reset. |
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0 |
LR0 |
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CorePac 0 reset status |
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0 |
= CorePac 0 has not received a local reset. |
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1 |
= CorePac 0 received a local reset. |
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End of Table 3-8 |
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68 |
Device Configuration |
Copyright 2010 Texas Instruments Incorporated |
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com |
SPRS691—November 2010 |
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3.3.8 Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The Reset Status Clear Register is shown in Figure 3-7 and described in Table 3-9.
Figure 3-7 Reset Status Clear Register (RESET_STAT_CLR)
31 |
30 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
GR |
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Reserved |
LR7 |
LR6 |
LR5 |
LR4 |
LR3 |
LR2 |
LR1 |
LR0 |
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RW, +0 |
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R, + 000 0000 0000 0000 0000 0000 |
RW,+0 |
RW,+0 |
RW,+0 |
RW,+0 |
RW,+0 |
RW,+0 |
RW,+0 |
RW,+0 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
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Table 3-9 |
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions |
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Bit |
Field |
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Description |
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31 |
GR |
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Global Reset Clear bit |
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0 |
= Writing a 0 has no effect. |
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1 |
= Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register. |
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30-8 |
Reserved |
Reserved. |
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7 |
LR7 |
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CorePac 7 reset Clear bit |
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0 |
= Writing a 0 has no effect. |
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1 |
= Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register. |
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6 |
LR6 |
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CorePac 6 reset Clear bit |
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0 |
= Writing a 0 has no effect. |
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1 |
= Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register. |
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5 |
LR5 |
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CorePac 5 reset Clear bit |
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0 |
= Writing a 0 has no effect. |
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1 |
= Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register. |
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4 |
LR4 |
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CorePac 4 reset Clear bit |
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0 |
= Writing a 0 has no effect. |
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1 |
= Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register. |
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3 |
LR3 |
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CorePac 3 reset Clear bit |
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0 |
= Writing a 0 has no effect. |
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1 |
= Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register. |
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2 |
LR2 |
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CorePac 2 reset Clear bit |
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0 |
= Writing a 0 has no effect. |
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1 |
= Writing a 1 to the LR2 bit clears the corresponding bit in the RESET_STAT register. |
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1 |
LR1 |
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CorePac 1 reset Clear bit |
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0 |
= Writing a 0 has no effect. |
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1 |
= Writing a 1 to the LR1 bit clears the corresponding bit in the RESET_STAT register. |
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0 |
LR0 |
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CorePac 0 reset Clear bit |
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0 |
= Writing a 0 has no effect. |
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1 |
= Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register. |
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End of Table 3-9 |
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ADVANCE INFORMATION
Copyright 2010 Texas Instruments Incorporated |
Device Configuration |
69 |