Микросхемотехника / amelina_m_a_amelin_s_a_programma_shemotehnicheskogo_modeliro

(ɫɬɨɥɛɟɰ ɧɟ ɩɨɞɫɨɟɞɢɧɹɟɬɫɹ ɤ ɜɵɯɨɞɧɨɦɭ ɜɟɧɬɢɥɸ). ȿɫɥɢ ɞɚɧɧɵɟ ɪɚɜɧɵ 1, ɫɨɨɬɜɟɬɫɬɜɭɸɳɢɣ ɜɯɨɞɧɨɣ ɫɬɨɥɛɟɰ ɩɨɞɤɥɸɱɚɟɬɫɹ ɤ ɜɟɧɬɢɥɸ. Ⱦɚɧɧɵɟ ɧɚɱɢɧɚ- ɸɬ ɡɚɩɢɫɵɜɚɬɶɫɹ ɫ ɧɭɥɟɜɨɝɨ ɚɞɪɟɫɚ. ɇɚɩɪɢɦɟɪ:

Ɇɚɬɪɢɰɵ ɫ ɩɪɹɦɵɦɢ ɜɯɨɞɚɦɢ TRUE ONLY (PLAND, PLOR, PLNAND, PLNOR, PLXOR, PLNXOR). ɇɭɥɟɜɨɣ ɚɞɪɟɫ ɨɛɨɡɧɚɱɚɟɬ ɩɟɪɜɵɣ ɜɯɨɞ, ɩɨɞɤɥɸ- ɱɟɧɧɵɣ (ɢɥɢ ɧɟɬ) ɤ ɩɟɪɜɨɦɭ ɜɵɯɨɞɧɨɦɭ ɜɟɧɬɢɥɸ. ɋɥɟɞɭɸɳɢɣ ɚɞɪɟɫ ɜ ɬɚɛɥɢɰɟ ɨɛɨɡɧɚɱɚɟɬ 2-ɨɣ ɜɯɨɞ ɉɅɆ ɩɨɞɤɥɸɱɟɧɧɵɣ (ɢɥɢ ɧɟɬ) ɤ ɩɟɪɜɨɦɭ ɜɵɯɨɞɧɨɦɭ ɜɟɧɬɢɥɸ ɢ ɬ.ɞ. ɞɨ ɬɟɯ ɩɨɪ, ɩɨɤɚ ɧɟ ɛɭɞɭɬ ɭɤɚɡɚɧɵ ɜɫɟ ɜɯɨɞɵ ɞɥɹ ɩɟɪɜɨɝɨ ɜɵ- ɯɨɞɧɨɝɨ ɜɟɧɬɢɥɹ. Ⱦɚɥɟɟ ɩɟɪɟɱɢɫɥɟɧɢɟ ɩɨɜɬɨɪɹɟɬɫɹ ɞɥɹ ɜɫɟɯ ɜɯɨɞɨɜ, ɩɨɞɤɥɸ- ɱɟɧɧɵɯ ɜɨ 2-ɦɭ ɜɵɯɨɞɧɨɦɭ ɜɟɧɬɢɥɸ ɢ ɬɚɤ ɞɨ ɬɟɯ ɩɨɪ, ɩɨɤɚ ɧɟ ɛɭɞɟɬ ɡɚɩɪɨ- ɝɪɚɦɦɢɪɨɜɚɧ ɩɨɫɥɟɞɧɢɣ ɜɵɯɨɞɧɨɣ ɜɟɧɬɢɥɶ.

Ɇɚɬɪɢɰɵ ɫ ɩɪɹɦɵɦɢ ɢ ɢɧɜɟɪɫɧɵɦɢ ɜɯɨɞɚɦɢ TRUE&COMPLEMENT (PLANDC, PLORC, PLNANDC, PLNORC, PLXORC, PLNXORC). ɉɪɨɝɪɚɦɦɢ-

ɪɭɸɬɫɹ ɩɨɞɨɛɧɵɦ ɠɟ ɨɛɪɚɡɨɦ, ɬɨɥɶɤɨ ɫ ɱɟɪɟɞɨɜɚɧɢɟɦ ɩɪɹɦɨɝɨ ɢ ɢɧɜɟɪɫɧɨɝɨ ɜɯɨɞɨɜ (ɫɦ. ɪɢɫ. 13.13), ɩɪɢɱɟɦ ɛɢɬ ɞɥɹ ɢɧɜɟɪɫɧɨɝɨ ɜɯɨɞɚ ɩɨɦɟɳɚɟɬɫɹ ɩɨɫɥɟ ɛɢɬɚ ɞɥɹ ɩɪɹɦɨɝɨ ɜɯɨɞɚ. ɉɨ ɧɭɥɟɜɨɦɭ ɚɞɪɟɫɭ ɬɚɛɥɢɰɵ ɩɨɦɟɳɚɟɬɫɹ ɩɟɪɜɵɣ ɩɪɹɦɨɣ ɜɯɨɞ ɩɨɞɫɨɟɞɢɧɟɧɧɵɣ «1» (ɢɥɢ ɧɟɬ «0») ɤ ɩɟɪɜɨɦɭ ɜɵɯɨɞɧɨɦɭ ɜɟɧɬɢ- ɥɸ. ɉɨ ɫɥɟɞɭɸɳɟɦɭ ɚɞɪɟɫɭ ɩɨɦɟɳɚɟɬɫɹ ɩɟɪɜɵɣ ɢɧɜɟɪɫɧɵɣ ɜɯɨɞ ɩɨɞɫɨɟɞɢ- ɧɟɧɧɵɣ «1» (ɢɥɢ ɧɟɬ «0») ɤɨ ɜɯɨɞɭ ɩɟɪɜɨɝɨ ɜɵɯɨɞɧɨɝɨ ɜɟɧɬɢɥɹ. Ɂɚɬɟɦ ɜɬɨɪɨɣ ɩɪɹɦɨɣ ɜɯɨɞ ɩɨɞɤɥɸɱɟɧɧɵɣ (ɢɥɢ ɧɟɬ) ɤ ɩɟɪɜɨɦɭ ɜɵɯɨɞɧɨɦɭ ɜɟɧɬɢɥɸ ɢ ɬɚɤ ɞɚ- ɥɟɟ ɞɨ ɬɟɯ ɩɨɪ, ɩɨɤɚ ɜɫɟ ɜɯɨɞɵ (ɩɪɹɦɵɟ ɢ ɢɧɜɟɪɫɧɵɟ) ɞɥɹ ɩɟɪɜɨɝɨ ɜɵɯɨɞɧɨɝɨ ɜɟɧɬɢɥɹ ɧɟ ɛɭɞɭɬ ɨɩɢɫɚɧɵ. Ɂɚɬɟɦ ɩɪɨɰɟɫɫ ɨɩɢɫɚɧɢɹ ɩɨɜɬɨɪɹɟɬɫɹ ɞɥɹ ɜɬɨɪɨɝɨ ɜɵɯɨɞɧɨɝɨ ɜɟɧɬɢɥɹ ɢ ɬɚɤ ɞɨ ɬɟɯ ɩɨɪ, ɩɨɤɚ ɩɨɫɥɟɞɧɢɣ ɜɵɯɨɞɧɨɣ ɜɟɧɬɢɥɶ ɧɟ ɛɭɞɟɬ ɡɚɩɪɨɝɪɚɦɦɢɪɨɜɚɧ.

Ɍɚɛɥɢɰɚ ɞɚɧɧɵɯ ɞɨɥɠɧɚ ɛɵɬɶ ɨɝɪɚɧɢɱɟɧɚ ɫ ɞɜɭɯ ɫɬɨɪɨɧ ɡɧɚɤɚɦɢ ($). Ɉɧɢ ɞɨɥɠɧɵ ɛɵɬɶ ɨɬɞɟɥɟɧɵ ɨɬ ɞɚɧɧɵɯ ɩɪɨɛɟɥɨɦ.

ɉɪɢɦɟɪɵ ɦɨɞɟɥɢɪɨɜɚɧɢɹ ɩɪɨɝɪɚɦɦɢɪɭɟɦɵɯ ɥɨɝɢɱɟɫɤɢɯ ɦɚɬɪɢɰ ɫɦ. ɜ

ɫɯɟɦɧɨɦ ɮɚɣɥɟ PLA3.CIR ɤɚɬɚɥɨɝɚ Components\Digital.

Ɏɨɪɦɚɬ ɞɢɪɟɤɬɢɜɵ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ (Timing Model) ɞɥɹ ɉɅɆ:

.MODEL <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> UPLD ([ɩɚɪɚɦɟɬɪɵ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ])

ɉɪɢɦɟɪ:

.MODEL PLD1 UPLD (TPLHMN=10ns TPLHTY=25ns TPLHMX=35ns)

13.2.9. Ɇɧɨɝɨɪɚɡɪɹɞɧɵɟ ɚɧɚɥɨɝɨ-ɰɢɮɪɨɜɵɟ ɩɪɟɨɛɪɚɡɨɜɚɬɟɥɢ

Ɏɨɪɦɚɬ SPICE

U<ɢɦɹ> ADC(<ɤɨɥɢɱɟɫɬɜɨ ɜɵɯɨɞɧɵɯ ɞɜɨɢɱɧɵɯ ɪɚɡɪɹɞɨɜ>) +<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ> +<ɚɧɚɥɨɝɨɜɵɣ ɜɯɨɞ> <ɨɩɨɪɧɨɟ ɧɚɩɪɹɠɟɧɢɟ> <ɨɛɳɢɣ> <ɡɚɩɭɫɤ> +<ɤɨɧɟɰ ɩɪɟɨɛɪɚɡɨɜɚɧɢɹ> <ɩɟɪɟɩɨɥɧɟɧɢɟ> +<ɜɵɯɨɞ ɫɬɚɪɲɟɝɨ ɛɢɬɚ>…<ɜɵɯɨɞ ɦɥɚɞɲɟɝɨ ɛɢɬɚ>

+<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ> +[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>] +[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>]

ɉɪɢɦɟɪɵ:

U10 ADC(8) $G_DPWR $G_DGND

+analog_in reference 0 convert status over B7 B6 B5 B4 B3 B2 B1 B0 +IO_STD_OC_ST

Ɏɨɪɦɚɬ ɫɯɟɦ Micro-Cap

xɬɪɢɛɭɬ PART: <ɢɦɹ>

xɬɪɢɛɭɬ TIMING MODEL: <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ>

xɬɪɢɛɭɬ I/O MODEL: <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

xɬɪɢɛɭɬ MNTYMXDLY: <ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>

xɬɪɢɛɭɬ IO_LEVEL: <ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>

xɬɪɢɛɭɬ POWER NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ>

xɬɪɢɛɭɬ GROUND NODE: < ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ >

ɋɨɞɟɪɠɢɬ ɫɬɚɧɞɚɪɬɧɵɟ ɚɬɪɢɛɭɬɵ, ɤɨɬɨɪɵɟ ɡɚɩɨɥɧɹɸɬɫɹ ɜ ɨɤɧɟ ɡɚɞɚɧɢɹ ɩɚɪɚɦɟɬɪɨɜ ɩɨ ɨɛɳɢɦ ɩɪɚɜɢɥɚɦ.

ɋɩɟɰɢɚɥɶɧɵɟ ɩɨɥɹ ɪɟɞɚɤɬɨɪɚ ɤɨɦɩɨɧɟɧɬɨɜ:

Address <ɤɨɥɢɱɟɫɬɜɨ ɜɵɯɨɞɧɵɯ ɞɜɨɢɱɧɵɯ ɪɚɡɪɹɞɨɜ>

ȼ ɪɟɞɚɤɬɨɪɟ ɤɨɦɩɨɧɟɧɬɨɜ ɢɦɟɟɬɫɹ ɫɩɟɰɢɚɥɶɧɨɟ ɩɨɥɟ Address ɞɥɹ ɚɧɚɥɨ- ɝɨ-ɰɢɮɪɨɜɵɯ ɩɪɟɨɛɪɚɡɨɜɚɬɟɥɟɣ. ȼ ɧɟɦ ɭɤɚɡɵɜɚɟɬɫɹ ɤɨɥɢɱɟɫɬɜɨ ɜɵɯɨɞɧɵɯ ɞɜɨɢɱɧɵɯ ɪɚɡɪɹɞɨɜ ɐɉ. ɉɪɢ ɜɜɨɞɟ ɜ ɩɨɥɟ ɫɨɨɬɜɟɬɫɬɜɭɸɳɟɝɨ ɡɧɚɱɟɧɢɹ, ɩɪɨ- ɝɪɚɦɦɚ ɩɨɦɟɳɚɟɬ ɞɨɩɨɥɧɢɬɟɥɶɧɵɟ ɜɵɜɨɞɵ ɜ ɨɤɧɨ ɩɪɨɪɢɫɨɜɤɢ ɤɨɦɩɨɧɟɧɬɚ, ɤɨɬɨɪɵɟ ɦɨɠɧɨ ɩɟɪɟɬɚɫɤɢɜɚɬɶ ɦɵɲɶɸ ɧɚ ɧɭɠɧɭɸ ɩɨɡɢɰɢɸ.

ȿɫɥɢ ɡɚɞɚɧ N-ɛɢɬɨɜɵɣ ɐɉ, ɬɨ ɜɵɯɨɞɧɵɯ ɜɵɜɨɞɨɜ ɛɭɞɟɬ N: Out0...OutN-1. ɐɉ ɩɪɟɨɛɪɚɡɭɟɬ ɚɧɚɥɨɝɨɜɨɟ ɧɚɩɪɹɠɟɧɢɟ ɦɟɠɞɭ ɭɡɥɚɦɢ <ɚɧɚɥɨɝɨɜɵɣ ɜɯɨɞ> ɢ <ɨɛɳɢɣ> ɜ ɰɢɮɪɨɜɨɣ ɷɤɜɢɜɚɥɟɧɬ. ɐɢɮɪɨɜɨɣ ɜɵɯɨɞɧɨɣ ɤɨɞ ɩɪɟɞɫɬɚɜɥɹɟɬ ɫɥɟɞɭɸɳɭɸ ɨɤɪɭɝɥɟɧɧɭɸ ɞɨ ɛɥɢɠɚɣɲɟɝɨ ɰɟɥɨɝɨ ɜɟɥɢɱɢɧɭ:

V in, gnd 2N . V ref , gnd

ȿɫɥɢ ɚɧɚɥɨɝɨɜɨɟ ɧɚɩɪɹɠɟɧɢɟ ɧɚ ɜɯɨɞɟ V(in, gnd) ɨɬɪɢɰɚɬɟɥɶɧɨ, ɬɨɝɞɚ ɜɫɟ ɜɵɯɨɞɧɵɟ ɛɢɬɵ ɞɚɧɧɵɯ ɭɫɬɚɧɨɜɹɬɫɹ ɜ 0, ɚ ɧɚ ɜɵɯɨɞɟ ɩɟɪɟɩɨɥɧɟɧɢɹ overrange ɭɫɬɚɧɨɜɢɬɫɹ 1. ȿɫɥɢ ɚɧɚɥɨɝɨɜɚɹ ɜɟɥɢɱɢɧɚ ɧɚ ɜɯɨɞɟ ɩɪɟɜɵɲɚɟɬ ɨɩɨɪɧɨɟ ɧɚɩɪɹɠɟɧɢɟ V(ref, gnd), ɬɨɝɞɚ ɜɫɟ ɛɢɬɵ ɞɚɧɧɵɯ ɭɫɬɚɧɨɜɹɬɫɹ ɜ 1, ɢ ɜɵɯɨɞ ɩɟɪɟ- ɩɨɥɧɟɧɢɹ ɬɚɤɠɟ ɭɫɬɚɧɨɜɢɬɫɹ ɜ 1.

ɉɪɟɨɛɪɚɡɨɜɚɧɢɟ ɜɯɨɞɧɨɝɨ ɚɧɚɥɨɝɨɜɨɝɨ ɧɚɩɪɹɠɟɧɢɹ ɧɚɱɢɧɚɟɬɫɹ ɩɨ ɩɟɪɟɞ- ɧɟɦɭ ɮɪɨɧɬɭ ɫɢɝɧɚɥɚ CONVERT. ɉɨɫɥɟ ɤɚɠɞɨɝɨ ɩɟɪɟɞɧɟɝɨ ɮɪɨɧɬɚ ɫɢɝɧɚɥɚ CONVERT ɫɨɜɟɪɲɚɟɬɫɹ ɬɨɥɶɤɨ ɨɞɧɨ ɚɧɚɥɨɝɨ-ɰɢɮɪɨɜɨɟ ɩɪɟɨɛɪɚɡɨɜɚɧɢɟ ɚɧɚ- ɥɨɝɨɜɨɝɨ ɜɯɨɞɧɨɝɨ ɧɚɩɪɹɠɟɧɢɹ. ɋɩɭɫɬɹ TPCS ɫɟɤɭɧɞ ɩɨɫɥɟ ɧɚɱɚɥɚ ɞɟɣɫɬɜɢɹ

ɮɪɨɧɬɚ CONVERT, ɰɢɮɪɨɜɵɟ ɜɵɯɨɞɵ ɩɟɪɟɯɨɞɹɬ ɜ ɧɟɨɩɪɟɞɟɥɟɧɧɵɟ ɫɨɫɬɨɹ- ɧɢɹ ɢ ɨɞɧɨɜɪɟɦɟɧɧɨ ɜɨɡɧɢɤɚɟɬ ɟɞɢɧɢɱɧɨɟ ɫɨɫɬɨɹɧɢɟ ɧɚ ɜɵɯɨɞɟ STATUS. ɋɩɭɫɬɹ TPSD ɫɟɤɭɧɞ ɩɨɫɥɟ ɧɚɱɚɥɚ ɩɟɪɟɞɧɟɝɨ ɮɪɨɧɬɚ ɫɢɝɧɚɥɚ STATUS ɜɵɯɨ- ɞɵ ɞɚɧɧɵɯ ɧɚɱɢɧɚɸɬ ɭɫɬɚɧɚɜɥɢɜɚɬɶɫɹ ɜ ɫɨɨɬɜɟɬɫɬɜɢɢ ɫ ɩɪɟɨɛɪɚɡɭɟɦɵɦ ɧɚ- ɩɪɹɠɟɧɢɟɦ, ɚ ɟɳɟ ɱɟɪɟɡ ɢɧɬɟɪɜɚɥ TPDS ɜɵɯɨɞ STATUS ɩɟɪɟɣɞɟɬ ɜ ɫɨɫɬɨɹ- ɧɢɟ «0», ɫɢɝɧɚɥɢɡɢɪɭɹ ɨ ɝɨɬɨɜɧɨɫɬɢ ɧɨɜɵɯ ɞɚɧɧɵɯ ɧɚ ɰɢɮɪɨɜɵɯ ɜɵɯɨɞɚɯ. Ɉɩɢɫɚɧɧɭɸ ɩɨɫɥɟɞɨɜɚɬɟɥɶɧɨɫɬɶ ɫɢɝɧɚɥɨɜ ɢɥɥɸɫɬɪɢɪɭɟɬ ɪɢɫ. 13.14.

Ɋɢɫ. 13.14. ȼɪɟɦɟɧɧɵɟ ɞɢɚɝɪɚɦɦɵ ɪɚɛɨɬɵ ɐɉ

Ɏɨɪɦɚɬ ɞɢɪɟɤɬɢɜɵ ɦɨɞɟɥɢ Ⱥɐɉ

.MODEL <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> UADC ([ɩɚɪɚɦɟɬɪɵ ɦɨɞɟɥɢ])

ɉɪɢɦɟɪ:

.MODEL A1 UADC (TPCSMN=5ns TPCSTY=15ns TPCSMX=25ns)

ɉɚɪɚɦɟɬɪɵ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ ɐɉ ɩɪɢɜɟɞɟɧɵ ɜ ɬɚɛɥ. 13.17.

Ɍ ɚ ɛ ɥ ɢ ɰ ɚ 1 3 . 1 7 . ɉɚɪɚɦɟɬɪɵ ɦɨɞɟɥɟɣ Ⱥɐɉ ɢ ɐȺɉ, ɫ

13.2.10. Ɇɧɨɝɨɪɚɡɪɹɞɧɵɟ ɰɢɮɪɨɚɧɚɥɨɝɨɜɵɟ ɩɪɟɨɛɪɚɡɨɜɚɬɟɥɢ

Ɏɨɪɦɚɬ SPICE

U<ɢɦɹ> DAC(<ɤɨɥɢɱɟɫɬɜɨ ɜɯɨɞɧɵɯ ɞɜɨɢɱɧɵɯ ɪɚɡɪɹɞɨɜ>) +<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ> +<ɚɧɚɥɨɝɨɜɵɣ ɜɵɯɨɞ> <ɨɩɨɪɧɨɟ ɧɚɩɪɹɠɟɧɢɟ> <ɨɛɳɢɣ> +<ɜɯɨɞ ɫɬɚɪɲɟɝɨ ɛɢɬɚ> <ɜɯɨɞ ɦɥɚɞɲɟɝɨ ɛɢɬɚ> +<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ> +[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>] +[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>]

ɉɪɢɦɟɪ:

U10 DAC(8) $G_DPWR $G_DGND

+analog_out reference 0 B7 B6 B5 B4 B3 B2 B1 B0 + D0_EFF IO_STD_ST

Ɏɨɪɦɚɬ ɫɯɟɦ Micro-Cap

xɬɪɢɛɭɬ PART: <ɢɦɹ>

xɬɪɢɛɭɬ TIMING MODEL: <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ>

xɬɪɢɛɭɬ I/O MODEL: <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

xɬɪɢɛɭɬ MNTYMXDLY: <ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>

xɬɪɢɛɭɬ IO_LEVEL: <ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>

xɬɪɢɛɭɬ POWER NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ>

xɬɪɢɛɭɬ GROUND NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ>

ɋɩɟɰɢɚɥɶɧɵɟ ɩɨɥɹ ɪɟɞɚɤɬɨɪɚ ɤɨɦɩɨɧɟɧɬɨɜ:

Address <ɤɨɥɢɱɟɫɬɜɨ ɜɯɨɞɧɵɯ ɞɜɨɢɱɧɵɯ ɪɚɡɪɹɞɨɜ>

Ɋɟɞɚɤɬɨɪ ɤɨɦɩɨɧɟɧɬɨɜ ɢɦɟɟɬ ɫɩɟɰɢɚɥɶɧɨɟ ɩɨɥɟ Address ɞɥɹ ɰɢɮɪɨɚɧɚ- ɥɨɝɨɜɵɯ ɩɪɟɨɛɪɚɡɨɜɚɬɟɥɟɣ. ȼ ɧɟɦ ɭɤɚɡɵɜɚɟɬɫɹ ɤɨɥɢɱɟɫɬɜɨ ɜɯɨɞɧɵɯ ɞɜɨɢɱɧɵɯ ɪɚɡɪɹɞɨɜ ɐ ɉ. ɉɪɢ ɜɜɨɞɟ ɜ ɩɨɥɟ ɫɨɨɬɜɟɬɫɬɜɭɸɳɟɝɨ ɡɧɚɱɟɧɢɹ, ɩɪɨɝɪɚɦɦɚ ɩɨ- ɦɟɳɚɟɬ ɞɨɩɨɥɧɢɬɟɥɶɧɵɟ ɜɵɜɨɞɵ ɜ ɨɤɧɨ ɩɪɨɪɢɫɨɜɤɢ ɤɨɦɩɨɧɟɧɬɚ, ɤɨɬɨɪɵɟ ɦɨɠɧɨ ɩɟɪɟɬɚɫɤɢɜɚɬɶ ɦɵɲɶɸ ɧɚ ɧɭɠɧɭɸ ɩɨɡɢɰɢɸ.

ɇɚɡɜɚɧɢɹ ɜɵɜɨɞɨɜ ɐ ɉ, ɩɪɢɫɜɚɢɜɚɟɦɵɟ ɪɟɞɚɤɬɨɪɨɦ ɤɨɦɩɨɧɟɧɬɨɜ:

ɐ ɉ ɩɪɟɨɛɪɚɡɭɟɬ ɞɟɫɹɬɢɱɧɵɣ ɷɤɜɢɜɚɥɟɧɬ ɞɜɨɢɱɧɨɝɨ ɜɯɨɞɧɨɝɨ ɤɨɞɚ ɜ ɚɧɚɥɨɝɨɜɨɟ ɜɵɯɨɞɧɨɟ ɧɚɩɪɹɠɟɧɢɟ ɦɟɠɞɭ ɭɡɥɚɦɢ <out> ɢ <gnd>. ɧɚɥɨɝɨɜɨɟ

ɧɚɩɪɹɠɟɧɢɟ ɧɚ ɜɵɯɨɞɟ ɞɥɹ n-ɛɢɬɧɨɝɨ ɜɯɨɞɧɨɝɨ ɤɨɞɚ bn-1,...b2, b0, ɛɭɞɟɬ ɨɩɪɟ- ɞɟɥɹɬɶɫɹ ɩɨ ɫɥɟɞɭɸɳɟɣ ɮɨɪɦɭɥɟ:

586 ɉɪɨɝɪ ɦɦ ɫɯɟɦɨɬɟɯɧɢɱɟɫɤɨɝɨ ɦɨɞɟɥɢɪɨɜ ɧɢɹ Micro-Cap. ȼɟɪɫɢɢ 9, 10

ɧɨɟ ɧɚɩɪɹɠɟɧɢɟ 0.5 ɜɟɫɚ ɫɨɨɬɜɟɬɫɬɜɭɸɳɟɝɨ ɪɚɡɪɹɞɚ, ɬ.ɟ. ɟɫɥɢ ɧɚ ɜɯɨɞɟ i ɭɪɨɜɟɧɶ «X», ɬɨ ɜɤɥɚɞ ɷɬɨɝɨ ɪɚɡɪɹɞɚ ɜ ɜɵɯɨɞɧɨɟ ɚɧɚɥɨɝɨɜɨɟ ɧɚɩɪɹɠɟɧɢɟ ɛɭ- ɞɟɬ ɨɩɪɟɞɟɥɹɬɶɫɹ ɩɨ ɫɥɟɞɭɸɳɟɣ ɮɨɪɦɭɥɟ:

ɉɪɢ ɢɡɦɟɧɟɧɢɢ ɰɢɮɪɨɜɨɝɨ ɤɨɞɚ ɧɚ ɜɯɨɞɚɯ ɐ ɉ, ɧɚɩɪɹɠɟɧɢɟ ɧɚ ɚɧɚɥɨɝɨ- ɜɨɦ ɜɵɯɨɞɟ ɛɭɞɟɬ ɢɡɦɟɧɹɬɶɫɹ ɩɨ ɥɢɧɟɣɧɨɦɭ ɡɚɤɨɧɭ ɨɬ ɩɪɟɞɵɞɭɳɟɝɨ ɚɧɚɥɨɝɨ- ɜɨɝɨ ɷɤɜɢɜɚɥɟɧɬɚ ɤ ɧɨɜɨɦɭ ɜ ɬɟɱɟɧɢɟ ɜɪɟɦɟɧɢ TSW (ɪɢɫ. 13.15).

Ɋɢɫ. 13.15. ȼɪɟɦɟɧɧɵɟ ɞɢɚɝɪɚɦɦɵ ɪɚɛɨɬɵ ɦɨɞɟɥɢ ɐ ɉ

Ɏɨɪɦɚɬ ɞɢɪɟɤɬɢɜɵ ɦɨɞɟɥɢ ɐȺɉ:

.MODEL <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> UDAC ([ɩɚɪɚɦɟɬɪɵ ɦɨɞɟɥɢ]).

ɉɪɢɦɟɪ:

.MODEL DAC1 UDAC (TSWMN=5ns TSWTY=15ns TSWMX=25ns)

Ⱦɥɹ ɢɥɥɸɫɬɪɚɰɢɢ ɪɚɛɨɬɵ ɦɨɞɟɥɟɣ ɐɉ ɢ ɐ ɉ ɫɦ. ɦɨɞɟɥɢɪɨɜɚɧɢɟ ɫɯɟɦ-

ɧɨɝɨ ɮɚɣɥɚ AD16.cir ɢɡ ɤɚɬɚɥɨɝɚ Components\Digital.

13.3. Ɏɭɧɤɰɢɨɧɚɥɶɧɵɟ ɰɢɮɪɨɜɵɟ ɛɥɨɤɢ

Ɏɭɧɤɰɢɨɧɚɥɶɧɵɟ ɰɢɮɪɨɜɵɟ ɛɥɨɤɢ ɭɩɪɨɳɚɸɬ ɦɨɞɟɥɢɪɨɜɚɧɢɟ ɫɥɨɠɧɵɯ ɰɢɮɪɨɜɵɯ ɭɫɬɪɨɣɫɬɜ. Ɉɧɢ ɫɨɫɬɨɹɬ ɢɡ ɬɪɟɯ ɪɚɡɧɨɜɢɞɧɨɫɬɟɣ:

Ʌɨɝɢɱɟɫɤɢɟ ɜɵɪɚɠɟɧɢɹ (Logic Expressions). ɉɨɜɟɞɟɧɢɟ ɷɬɢɯ ɛɥɨɤɨɜ ɨɩɢɫɵɜɚɟɬɫɹ ɫ ɩɨɦɨɳɶɸ ɥɨɝɢɱɟɫɤɢɯ ɜɵɪɚɠɟɧɢɣ.

Ɂɚɞɟɪɠɤɚ ɪɚɫɩɪɨɫɬɪɚɧɟɧɢɹ ɫɢɝɧɚɥɚ ɦɟɠɞɭ ɞɜɭɦɹ ɭɡɥɚɦɢ (Pin-to-pin delays) [3, 6]. ɉɨɡɜɨɥɹɟɬ ɡɚɞɚɜɚɬɶ ɩɪɚɜɢɥɚ ɜɵɱɢɫɥɟɧɢɹ ɡɚɞɟɪɠɟɤ ɪɚɫɩɪɨɫɬɪɚ- ɧɟɧɢɹ ɫɢɝɧɚɥɚ ɦɟɠɞɭ ɞɜɭɦɹ ɜɵɜɨɞɚɦɢ. ɍɤɚɡɚɧɧɵɟ ɩɪɚɜɢɥɚ ɩɪɟɞɫɬɚɜɥɹɸɬ ɫɨ- ɛɨɣ ɥɨɝɢɱɟɫɤɢɟ ɜɵɪɚɠɟɧɢɹ, ɨɫɧɨɜɚɧɧɵɟ ɧɚ ɫɜɨɣɫɬɜɚɯ ɜɯɨɞɨɜ ɛɥɨɤɚ.

Ȼɥɨɤɢ ɩɪɨɜɟɪɤɢ ɜɪɟɦɟɧɧɵɯ ɫɨɨɬɧɨɲɟɧɢɣ (Constraints) [3, 6]. ɉɨɡɜɨ-

ɥɹɸɬ ɩɪɨɜɟɪɢɬɶ ɫɨɛɥɸɞɟɧɢɟ ɜɪɟɦɟɧɧɵɯ ɨɝɪɚɧɢɱɟɧɢɣ ɢ ɜɵɞɚɬɶ ɩɪɟɞɭɩɪɟɠ- ɞɚɸɳɢɟ ɫɨɨɛɳɟɧɢɹ ɜ ɫɥɭɱɚɟ ɢɯ ɧɚɪɭɲɟɧɢɹ. ȼɪɟɦɟɧɧɵɟ ɨɝɪɚɧɢɱɟɧɢɹ ɜɤɥɸ- ɱɚɸɬ ɦɢɧɢɦɚɥɶɧɭɸ ɞɥɢɬɟɥɶɧɨɫɬɶ ɢɦɩɭɥɶɫɚ (pulse width), ɦɚɤɫɢɦɚɥɶɧɭɸ ɱɚɫ- ɬɨɬɭ ɢɦɩɭɥɶɫɨɜ, ɜɪɟɦɹ ɭɫɬɚɧɨɜɤɢ ɬɪɢɝɝɟɪɚ, ɜɪɟɦɹ ɭɞɟɪɠɚɧɢɹ ɫɢɝɧɚɥɚ ɢ ɞɪɭɝɢɟ ɨɝɪɚɧɢɱɟɧɢɹ, ɨɩɪɟɞɟɥɹɟɦɵɟ ɩɨɥɶɡɨɜɚɬɟɥɟɦ.

ɉɟɪɟɱɢɫɥɟɧɧɵɟ ɛɥɨɤɢ ɲɢɪɨɤɨ ɢɫɩɨɥɶɡɭɸɬɫɹ ɜ ɛɢɛɥɢɨɬɟɤɟ ɰɢɮɪɨɜɵɯ ɢɧ- ɬɟɝɪɚɥɶɧɵɯ ɫɯɟɦ ɩɪɨɝɪɚɦɦɵ Micro-Cap (Digital Library). ɋɥɟɞɨɜɚɬɟɥɶɧɨ, ɧɟɬ ɨɫɨɛɨɣ ɧɟɨɛɯɨɞɢɦɨɫɬɢ ɨɜɥɚɞɟɜɚɬɶ ɩɪɚɜɢɥɚɦɢ ɢɯ ɩɨɫɬɪɨɟɧɢɹ, ɩɨɫɤɨɥɶɤɭ ɦɨɠ- ɧɨ ɩɪɨɫɬɨ ɢɫɩɨɥɶɡɨɜɚɬɶ ɦɨɞɟɥɢ ɧɟɨɛɯɨɞɢɦɨɣ ɫɟɪɢɢ ɢɧɬɟɝɪɚɥɶɧɵɯ ɫɯɟɦ. Ɉɞ- ɧɚɤɨ, ɟɫɥɢ ɧɟɨɛɯɨɞɢɦɨ ɩɨɫɬɪɨɢɬɶ ɦɨɞɟɥɶ ɰɢɮɪɨɜɨɝɨ ɤɨɦɩɨɧɟɧɬɚ, ɤɨɬɨɪɨɝɨ ɧɟɬ ɜ ɛɢɛɥɢɨɬɟɤɟ Digital Library, ɬɨ ɢɧɮɨɪɦɚɰɢɹ, ɩɪɢɜɟɞɟɧɧɚɹ ɧɢɠɟ, ɦɨɠɟɬ ɨɤɚɡɚɬɶɫɹ ɜɨɫɬɪɟɛɨɜɚɧɧɨɣ.

13.3.1. Ʌɨɝɢɱɟɫɤɢɟ ɜɵɪɚɠɟɧɢɹ (Logic Expressions)

ɉɪɢɦɢɬɢɜ logic expression ɩɨɡɜɨɥɹɟɬ ɨɩɢɫɚɬɶ ɩɨɜɟɞɟɧɢɟ ɞɨɫɬɚɬɨɱɧɨ ɫɥɨɠɧɨɝɨ ɰɢɮɪɨɜɨɝɨ ɭɫɬɪɨɣɫɬɜɚ. ɉɨɡɜɨɥɹɟɬ ɨɩɪɟɞɟɥɢɬɶ ɜɵɯɨɞɧɵɟ ɫɢɝɧɚɥɵ ɮɭɧɤɰɢɹɦɢ ɫɬɚɧɞɚɪɬɧɨɣ ɛɭɥɟɜɨɣ ɚɥɝɟɛɪɵ, ɢɫɩɨɥɶɡɭɹ ɜ ɤɚɱɟɫɬɜɟ ɩɟɪɟɦɟɧɧɵɯ ɞɥɹ ɷɬɢɯ ɜɵɪɚɠɟɧɢɣ ɜɯɨɞɧɵɟ ɫɨɫɬɨɹɧɢɹ, ɜɪɟɦɟɧɧɵɟ ɫɨɫɬɨɹɧɢɹ ɢ ɜɵɯɨɞɧɵɟ ɫɨɫɬɨɹɧɢɹ.

Ɏɨɪɦɚɬ SPICE:

U<ɢɦɹ> LOGICEXP(<ɤɨɥ. ɜɯɨɞɨɜ>,<ɤɨɥ. ɜɵɯɨɞɨɜ>) +<ɭɡɟɥ ɰɢɮɪɨɜɨɝɨ ɩɢɬɚɧɢɹ> <ɭɡɟɥ ɰɢɮɪɨɜɨɣ ɡɟɦɥɢ> +<ɩɟɪɜɵɣ ɜɯɨɞɧɨɣ ɭɡɟɥ>...<ɩɨɫɥɟɞɧɢɣ ɜɯɨɞɧɨɣ ɭɡɟɥ> +<ɩɟɪɜɵɣ ɜɵɯɨɞɧɨɣ ɭɡɟɥ>...<ɩɨɫɥɟɞɧɢɣ ɜɵɯɨɞɧɨɣ ɭɡɟɥ> +<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> +<ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

+[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɜɪɟɦɟɧɧɨɣ ɡɚɞɟɪɠɤɢ>] +[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>] + LOGIC:<ɥɨɝɢɱɟɫɤɢɟ ɜɵɪɚɠɟɧɢɹ>*

Ɏɨɪɦɚɬ ɫɯɟɦ Micro-Cap:

xɬɪɢɛɭɬ PART: <ɢɦɹ>

xɬɪɢɛɭɬ TIMING MODEL: <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ>

xɬɪɢɛɭɬ I/O MODEL: <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

xɬɪɢɛɭɬ LOGIC: LOGIC:{<ɥɨɝɢɱɟɫɤɨɟ ɜɵɪɚɠɟɧɢɟ>}

xɬɪɢɛɭɬ MNTYMXDLY: <ɫɟɥɟɤɬɨɪ ɜɪɟɦɟɧɧɨɣ ɡɚɞɟɪɠɤɢ>

xɬɪɢɛɭɬ IO_LEVEL: <ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>

xɬɪɢɛɭɬ POWER NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ>

xɬɪɢɛɭɬ GROUND NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ>

Ʉɨɦɩɨɧɟɧɬɵ ɬɢɩɚ Logic expressions ɨɛɵɱɧɨ ɫɨɡɞɚɸɬɫɹ ɜ ɜɢɞɟ ɬɟɤɫɬɨɜɨɝɨ SPICE-ɮɚɣɥɚ. Ɉɧɢ ɧɟ ɱɚɫɬɨ ɢɫɩɨɥɶɡɭɸɬɫɹ ɜ ɜɢɞɟ ɫɯɟɦɧɨɝɨ ɤɨɦɩɨɧɟɧɬɚ, ɨɞɧɚ- ɤɨ ɬɚɤɢɟ ɫɥɭɱɚɢ ɟɫɬɶ (Logic2X1, Logic2X2). ɂɦɟɧɧɨ ɷɬɢ ɩɪɢɦɢɬɢɜɵ c ɥɨɝɢɱɟ- ɫɤɢɦɢ ɜɵɪɚɠɟɧɢɹɦɢ ɜɤɥɸɱɟɧɵ ɜ ɛɢɛɥɢɨɬɟɤɭ ɤɨɦɩɨɧɟɧɬɨɜ Micro-Cap.

Ʉɚɤ ɜɢɞɧɨ, ɚɬɪɢɛɭɬ, ɫɩɟɰɢɮɢɱɧɵɣ ɞɥɹ ɪɚɫɫɦɚɬɪɢɜɚɟɦɨɝɨ ɤɨɦɩɨɧɟɧɬɚ — LOGIC. ȼɫɟ ɨɫɬɚɥɶɧɵɟ ɚɬɪɢɛɭɬɵ ɫɬɚɧɞɚɪɬɧɵɟ ɢ ɩɨɜɬɨɪɹɸɬ ɩɟɪɟɱɢɫɥɟɧɧɵɟ ɪɚɧɟɟ ɩɪɢ ɨɩɢɫɚɧɢɢ ɥɨɝɢɱɟɫɤɢɯ ɷɥɟɦɟɧɬɨɜ.

Ɂɧɚɱɟɧɢɟ ɚɬɪɢɛɭɬɚ ɩɪɟɞɫɬɚɜɥɹɟɬ ɫɨɛɨɣ ɩɨɥɧɨɟ ɥɨɝɢɱɟɫɤɨɟ ɜɵɪɚɠɟɧɢɟ ɢɥɢ ɟɝɨ ɢɦɹ, ɪɚɫɤɪɵɬɨɟ ɜ ɬɟɤɫɬɨɜɨɣ ɨɛɥɚɫɬɢ ɞɢɪɟɤɬɢɜɨɣ .DEFINE. ɋɥɟɞɭɟɬ ɨɬɦɟɬɢɬɶ ɨɛɹɡɚɬɟɥɶɧɨɟ ɩɪɢɫɭɬɫɬɜɢɟ ɤɥɸɱɟɜɨɝɨ ɫɥɨɜɚ 'LOGIC:' ɩɟɪɟɞ {<ɥɨɝɢ-

ɱɟɫɤɢɦ ɜɵɪɚɠɟɧɢɟɦ>}.

ɉɪɢɦɟɪɵ ɡɚɩɨɥɧɟɧɢɹ ɩɨɥɟɣ ɚɬɪɢɛɭɬɚ LOGIC:

588 ɉɪɨɝɪ ɦɦ ɫɯɟɦɨɬɟɯɧɢɱɟɫɤɨɝɨ ɦɨɞɟɥɢɪɨɜ ɧɢɹ Micro-Cap. ȼɟɪɫɢɢ 9, 10

LOFEXP1 ;ɞɨɥɠɧɨ ɛɵɬɶ ɨɩɪɟɞɟɥɟɧɨ ɞɢɪɟɤɬɢɜɨɣ .define ɜ ɬɟɤɫɬɨɜɨɣ ɨɛ-

ɥɚɫɬɢ

LOGIC: C= {A | B & C } ; ɨɛɹɡɚɬɟɥɶɧɨ ɤɥɸɱɟɜɨɟ ɫɥɨɜɨ 'LOGIC:' LOGIC: TEMP11 = {IN1 ^ IN2 & IN3 ^ IN4 }

LOGIC: TEMP12 = {IN1 ^ IN2 | IN3 ^ IN4 }

LOGIC: OUT1 = { TEMP11 & TEMP12 }

ɋɩɟɰɢɚɥɶɧɵɟ ɩɨɥɹ ɞɥɹ ɪɟɞɚɤɬɨɪɚ ɤɨɦɩɨɧɟɧɬɨɜ

Pins <ɱɢɫɥɨ ɜɯɨɞɨɜ, ɱɢɫɥɨ ɜɵɯɨɞɨɜ>

Ɋɟɞɚɤɬɨɪ ɤɨɦɩɨɧɟɧɬɨɜ Micro-Cap (Component editor) ɢɦɟɟɬ ɫɩɟɰɢɚɥɶɧɨɟ ɩɨɥɟ 'Pins' ɞɥɹ ɪɚɫɫɦɚɬɪɢɜɚɟɦɨɝɨ ɤɥɚɫɫɚ ɛɥɨɤɨɜ. ɗɬɨ ɩɨɥɟ ɧɟɥɶɡɹ ɪɟɞɚɤɬɢɪɨ- ɜɚɬɶ ɧɟɩɨɫɪɟɞɫɬɜɟɧɧɨ. ȼɦɟɫɬɨ ɷɬɨɝɨ ɧɟɨɛɯɨɞɢɦɨ ɳɟɥɤɧɭɬɶ ɦɵɲɶɸ ɢ ɩɪɨɫɬɨ ɞɨɛɚɜɢɬɶ ɜɯɨɞɧɨɣ ɢɥɢ ɜɵɯɨɞɧɨɣ ɜɵɜɨɞ.

Ɍɟɩɟɪɶ ɨ ɬɨɦ, ɤɚɤ ɫɥɟɞɭɟɬ ɨɩɪɟɞɟɥɹɬɶ ɢɦɟɧɚ ɢ ɪɚɫɩɨɥɨɠɟɧɢɟ ɜɵɜɨɞɨɜ ɞɚɧɧɵɯ ɤɨɦɩɨɧɟɧɬɨɜ. Ⱦɚɧɧɵɟ ɤɨɦɩɨɧɟɧɬɵ ɢɫɩɨɥɶɡɭɸɬɫɹ ɩɪɟɢɦɭɳɟɫɬɜɟɧɧɨ ɞɥɹ ɦɨɞɟɥɢɪɨɜɚɧɢɹ ɪɟɚɥɶɧɵɯ ɫɟɪɢɣ ɂɋ, ɩɨɷɬɨɦɭ ɯɪɚɧɹɬɫɹ ɝɥɚɜɧɵɦ ɨɛɪɚɡɨɦ ɜ ɜɢɞɟ ɩɨɞɫɯɟɦ ɜ ɬɟɤɫɬɨɜɵɯ ɛɢɛɥɢɨɬɟɱɧɵɯ SPICE-ɮɚɣɥɚɯ. ɉɨɫɤɨɥɶɤɭ ɜɫɟ ɨɧɢ ɢɦɟɸɬ ɪɚɡɥɢɱɧɨɟ ɤɨɥɢɱɟɫɬɜɨ ɜɯɨɞɧɵɯ ɢ ɜɵɯɨɞɧɵɯ ɜɵɜɨɞɨɜ, ɬɨ ɢɫɩɨɥɶɡɭɟɬɫɹ ɧɟɨɝɪɚɧɢɱɟɧɧɨɟ ɤɨɥɢɱɟɫɬɜɨ ɤɨɦɛɢɧɚɰɢɣ ɜɵɜɨɞɨɜ ɞɥɹ ɮɨɪɦɢɪɨɜɚɧɢɹ ɥɨɝɢɱɟ- ɫɤɢɯ ɮɭɧɤɰɢɣ. Ɍɚɤ ɤɚɤ ɤɨɦɩɨɧɟɧɬ ɜ ɛɢɛɥɢɨɬɟɤɟ ɤɨɦɩɨɧɟɧɬɨɜ ɬɪɟɛɭɟɬ ɭɤɚɡɚɧɢɹ ɢɦɟɧ ɢ ɪɚɫɩɨɥɨɠɟɧɢɹ ɜɵɜɨɞɨɜ, ɪɚɡɦɟɳɟɧɢɟ ɩɪɢɦɢɬɢɜɚ ɫ ɩɪɨɢɡɜɨɥɶɧɵɦ ɥɨ- ɝɢɱɟɫɤɨɣ ɮɭɧɤɰɢɟɣ ɜ ɛɢɛɥɢɨɬɟɤɟ ɧɟɜɨɡɦɨɠɧɨ. ɉɨɷɬɨɦɭ ɜ ɫɨɫɬɚɜɟ ɛɢɛɥɢɨɬɟɤɢ ɢɦɟɸɬɫɹ ɬɨɥɶɤɨ 2 ɩɨɞɨɛɧɵɯ ɤɨɦɩɨɧɟɧɬɚ (Logic2x1, Logic2x2) ɢ ɬɨ, ɝɥɚɜɧɵɦ ɨɛɪɚɡɨɦ, ɞɥɹ ɢɥɥɸɫɬɪɚɬɢɜɧɵɯ ɰɟɥɟɣ.

Ɉcɧɨɜɧɨɟ ɧɚɡɧɚɱɟɧɢɟ ɤɨɦɩɨɧɟɧɬɨɜ logic expression — ɢɫɩɨɥɶɡɨɜɚɧɢɟ ɜ ɫɨɫɬɚɜɟ ɬɟɤɫɬɨɜɨɝɨ ɮɚɣɥɚ ɛɢɛɥɢɨɬɟɤɢ Digital Library. ɉɨɫɤɨɥɶɤɭ ɤɨɦɩɨɧɟɧɬɵ ɢɡ ɷɬɨɣ ɛɢɛɥɢɨɬɟɤɢ ɦɨɝɭɬ ɢɫɩɨɥɶɡɨɜɚɬɶɫɹ ɜ ɫɨɫɬɚɜɟ ɦɨɞɟɥɢɪɭɟɦɵɯ ɫɯɟɦ ɧɟ- ɩɨɫɪɟɞɫɬɜɟɧɧɨ, ɪɟɚɥɶɧɚɹ ɦɨɳɶ ɷɥɟɦɟɧɬɨɜ logic expression ɩɪɨɹɜɥɹɟɬɫɹ ɩɪɢ ɫɨɡɞɚɧɢɢ ɦɨɞɟɥɟɣ ɤɨɦɦɟɪɱɟɫɤɢɯ ɢɧɬɟɝɪɚɥɶɧɵɯ ɫɯɟɦ (ɞɟɲɢɮɪɚɬɨɪɨɜ, ɦɭɥɶ- ɬɢɩɥɟɤɫɨɪɨɜ, Ʌɍ ɢ ɬ.ɩ.).

Ɏɨɪɦɚɬ ɥɨɝɢɱɟɫɤɢɯ ɜɵɪɚɠɟɧɢɣ

LOGIC. Ɉɬɦɟɱɚɟɬ ɧɚɱɚɥɨ ɨɞɧɨɝɨ (ɢɥɢ ɫɟɪɢɢ) ɥɨɝɢɱɟɫɤɢɯ ɜɵɪɚɠɟɧɢɣ. <ɥɨɝɢɱɟɫɤɨɟ ɜɵɪɚɠɟɧɢɟ> ɢɦɟɟɬ ɨɞɧɭ ɢɡ ɫɥɟɞɭɸɳɢɯ ɮɨɪɦ: <ɩɪɨɦɟɠɭɬɨɱɧɚɹ ɩɟɪɟɦɟɧɧɚɹ>={<ɥɨɝɢɱɟɫɤɨɟ ɜɵɪɚɠɟɧɢɟ>} <ɢɦɹ ɜɵɯɨɞɧɨɝɨ ɭɡɥɚ>={<ɥɨɝɢɱɟɫɤɨɟ ɜɵɪɚɠɟɧɢɟ>}

<ɩɪɨɦɟɠɭɬɨɱɧɚɹ ɩɟɪɟɦɟɧɧɚɹ> — ɩɟɪɟɦɟɧɧɚɹ, ɡɧɚɱɟɧɢɟ ɤɨɬɨɪɨɣ ɧɟ ɢɫɩɨɥɶɡɭɟɬɫɹ ɞɥɹ ɮɭɧɤɰɢɢ ɜɵɯɨɞɧɨɝɨ ɭɡɥɚ ɤɨɦɩɨɧɟɧɬɚ, ɫɨɡɞɚɟɬɫɹ ɞɥɹ ɜɪɟ- ɦɟɧɧɨɝɨ ɢɫɩɨɥɶɡɨɜɚɧɢɹ ɜ ɩɪɨɦɟɠɭɬɨɱɧɵɯ <ɥɨɝɢɱɟɫɤɢɯ ɜɵɪɚɠɟɧɢɹɯ>. ɂɫɩɨɥɶ-

ɡɨɜɚɧɢɟ ɩɪɨɦɟɠɭɬɨɱɧɵɯ ɩɟɪɟɦɟɧɧɵɯ ɭɩɪɨɳɚɟɬ ɢ ɭɥɭɱɲɚɟɬ ɱɢɬɚɛɟɥɶɧɨɫɬɶ ɢ ɩɨɧɢɦɚɧɢɟ ɥɨɝɢɱɟɫɤɨɣ ɮɭɧɤɰɢɢ ɤɨɦɩɨɧɟɧɬɚ ɤɚɤ ɟɞɢɧɨɝɨ ɰɟɥɨɝɨ, ɬɚɤɠɟ ɩɨɡɜɨ- ɥɹɟɬ ɫɧɢɡɢɬɶ ɤɨɥɢɱɟɫɬɜɨ ɜɨɡɦɨɠɧɵɯ ɨɲɢɛɨɤ.

<ɢɦɹ ɜɵɯɨɞɧɨɝɨ ɭɡɥɚ> — ɢɦɹ ɨɞɧɨɝɨ ɢɡ ɜɵɯɨɞɧɵɯ ɭɡɥɨɜ. ɉɪɢɫɜɨɟɧɢɟ ɞɚɧɧɨɦɭ ɭɡɥɭ <ɥɨɝɢɱɟɫɤɨɝɨ ɜɵɪɚɠɟɧɢɹ> ɩɪɢɜɟɞɟɬ ɤ ɮɨɪɦɢɪɨɜɚɧɢɸ ɟɝɨ ɧɚ ɞɚɧɧɨɦ ɜɵɯɨɞɧɨɦ ɜɵɜɨɞɟ ɫ ɜɪɟɦɟɧɧɵɦɢ ɩɚɪɚɦɟɬɪɚɦɢ, ɨɩɪɟɞɟɥɹɟɦɵɦɢ ɜɪɟ-

ɦɟɧɧɨɣ ɦɨɞɟɥɶɸ (timing model).

<ɥɨɝɢɱɟɫɤɨɟ ɜɵɪɚɠɟɧɢɟ> — ɩɪɨɢɡɜɨɥɶɧɨɟ ɥɨɝɢɱɟɫɤɨɟ ɜɵɪɚɠɟɧɢɟ, ɡɚ- ɩɢɫɚɧɧɨɟ ɜ ɫɨɨɬɜɟɬɫɬɜɢɢ ɫ ɩɪɚɜɢɥɚɦɢ, ɭɤɚɡɚɧɧɵɦɢ ɜ ɬɚɛɥ. 13.18, ɩɪɢɧɢɦɚɸ-

ɳɟɟ ɜ ɡɚɜɢɫɢɦɨɫɬɢ ɨɬ ɫɨɫɬɨɹɧɢɹ ɜɯɨɞɹɳɢɯ ɜ ɧɟɝɨ ɩɟɪɟɦɟɧɧɵɯ ɨɞɧɨ ɢɡ ɫɥɟ- ɞɭɸɳɢɯ ɩɹɬɢ ɰɢɮɪɨɜɵɯ ɭɪɨɜɧɟɣ {0, 1, R, F, X}. ȼɵɪɚɠɟɧɢɟ ɞɨɥɠɧɨ ɛɵɬɶ ɡɚ- ɤɥɸɱɟɧɨ ɜ ɮɢɝɭɪɧɵɟ ɫɤɨɛɤɢ. ȿɫɥɢ ɜɵɪɚɠɟɧɢɟ ɫɥɢɲɤɨɦ ɞɥɢɧɧɨɟ, ɟɝɨ ɦɨɠɧɨ ɩɟɪɟɧɨɫɢɬɶ ɧɚ ɫɥɟɞɭɸɳɭɸ ɫɬɪɨɤɭ, ɢɫɩɨɥɶɡɭɹ ɜ ɟɟ ɧɚɱɚɥɟ ɫɢɦɜɨɥ ɩɪɨɞɨɥɠɟ- ɧɢɹ ɩɪɟɞɵɞɭɳɟɣ ɫɬɪɨɤɢ (+).

Ɉɩɟɪɚɧɞɚɦɢ ɥɨɝɢɱɟɫɤɨɝɨ ɜɵɪɚɠɟɧɢɹ ɦɨɝɭɬ ɛɵɬɶ:

x<ɜɯɨɞɧɵɟ ɭɡɥɵ>

xɊɚɧɟɟ ɨɩɪɟɞɟɥɟɧɧɵɟ <ɩɪɨɦɟɠɭɬɨɱɧɵɟ ɩɟɪɟɦɟɧɧɵɟ>

xɊɚɧɟɟ ɨɩɪɟɞɟɥɟɧɧɵɟ <ɜɵɯɨɞɧɵɟ ɭɡɥɵ>

xɅɨɝɢɱɟɫɤɢɟ ɤɨɧɫɬɚɧɬɵ: '0, '1, 'R, 'F, ɢ 'X. ɂɦɟɧɚɦ ɩɨɫɬɨɹɧɧɵɯ ɥɨɝɢɱɟɫɤɢɯ ɫɨɫɬɨɹɧɢɣ (ɤɨɧɫɬɚɧɬ) ɨɛɹɡɚɬɟɥɶɧɨ ɩɪɟɞɲɟɫɬɜɭɟɬ ɚɩɨɫɬɪɨɮ.

Ʉɪɭɝɥɵɟ ɫɤɨɛɤɢ ɬɚɤɠɟ ɦɨɝɭɬ ɢɫɩɨɥɶɡɨɜɚɬɶɫɹ ɩɪɢ ɡɚɩɢɫɢ ɥɨɝɢɱɟɫɤɢɯ ɜɵɪɚ-

ɠɟɧɢɣ.

Ɍ ɚ ɛ ɥ ɢ ɰ ɚ 1 3 . 1 8 . Ɉɛɨɡɧɚɱɟɧɢɹ ɥɨɝɢɱɟɫɤɢɯ ɨɩɟɪɚɰɢɣ

Ɏɨɪɦɚɬ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ (Timing model)

ȼɪɟɦɟɧɧɚɹ ɦɨɞɟɥɶ ɢɦɟɟɬ ɫɬɚɧɞɚɪɬɧɵɣ ɮɨɪɦɚɬ ɞɥɹ ɜɟɧɬɢɥɹ UGATE.

.MODEL <ɢɦɹ ɦɨɞɟɥɢ> UGATE ([ɩɚɪɚɦɟɬɪɵ ɦɨɞɟɥɢ])

ɉɨɜɟɞɟɧɢɟ ɤɨɦɩɨɧɟɧɬɚ ɩɪɢ ɦɨɞɟɥɢɪɨɜɚɧɢɢ. ɋɟɪɢɹ ɨɩɟɪɚɬɨɪɨɜ, ɪɚɫ-

ɩɨɥɨɠɟɧɧɚɹ ɡɚ ɤɥɸɱɟɜɵɦ ɫɥɨɜɨɦ LOGIC, ɜɵɩɨɥɧɹɟɬɫɹ ɩɪɢ ɤɚɠɞɨɦ ɢɡɦɟɧɟɧɢɢ ɰɢɮɪɨɜɨɝɨ ɫɨɫɬɨɹɧɢɹ ɥɸɛɨɝɨ ɜɯɨɞɧɨɝɨ (ɜɵɯɨɞɧɨɝɨ) ɜɵɜɨɞɚ ɤɨɦɩɨɧɟɧɬɚ.

Ʉɚɠɞɵɣ ɨɩɟɪɚɬɨɪ ɥɨɝɢɱɟɫɤɨɝɨ ɩɪɢɫɜɚɢɜɚɧɢɹ ɜɵɱɢɫɥɹɟɬɫɹ ɜ ɩɨɪɹɞɤɟ ɪɚɫ- ɩɨɥɨɠɟɧɢɹ ɟɝɨ ɜ ɷɬɨɦ ɛɥɨɤɟ. ȼɵɪɚɠɟɧɢɹ ɜ ɨɩɟɪɚɬɨɪɚɯ ɧɟ ɢɦɟɸɬ ɜɪɟɦɟɧɧɵɯ ɡɚɞɟɪɠɟɤ, ɡɚ ɢɫɤɥɸɱɟɧɢɟɦ ɨɩɟɪɚɬɨɪɨɜ ɩɪɢɫɜɚɢɜɚɧɢɹ ɡɧɚɱɟɧɢɣ ɜɵɯɨɞɧɵɦ ɭɡ- ɥɚɦ. Ɂɧɚɱɟɧɢɟ ɮɭɧɤɰɢɢ ɜ ɥɸɛɨɦ ɜɵɯɨɞɧɨɦ ɭɡɥɟ ɚɫɫɨɰɢɢɪɭɟɬɫɹ ɫ ɜɪɟɦɟɧɧɵ- ɦɢ ɡɚɞɟɪɠɤɚɦɢ ɢɡ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ. ɋɥɟɞɭɟɬ ɨɬɦɟɬɢɬɶ, ɱɬɨ ɨɛɵɱɧɨ ɜɫɟ ɡɚ- ɞɟɪɠɤɢ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ ɭɫɬɚɧɚɜɥɢɜɚɸɬɫɹ ɜ ɧɭɥɟɜɨɟ ɡɧɚɱɟɧɢɟ. ȼɦɟɫɬɨ ɧɢɯ, ɪɟɚɥɶɧɵɟ ɡɚɞɟɪɠɤɢ ɰɢɮɪɨɜɨɝɨ ɤɨɦɩɨɧɟɧɬɚ ɢɡ ɛɢɛɥɢɨɬɟɤɢ ɦɨɞɟɥɢɪɭɸɬɫɹ ɩɨ- ɫɬɚɧɨɜɤɨɣ ɜɵɯɨɞɧɨɝɨ ɛɭɮɟɪɚ — ɤɨɦɩɨɧɟɧɬɚ pin-to-pin delay. ɗɬɢ ɤɨɦɩɨɧɟɧɬɵ ɨɛɟɫɩɟɱɢɜɚɸɬ ɥɨɝɢɱɟɫɤɨɟ ɭɩɪɚɜɥɟɧɢɟ ɡɚɞɟɪɠɤɚɦɢ, ɢɫɩɨɥɶɡɭɹ ɫɩɪɚɜɨɱɧɵɟ ɩɚɪɚɦɟɬɪɵ ɦɢɤɪɨɫɯɟɦɵ. ɉɪɢ ɷɬɨɦ ɜɧɭɬɪɟɧɧɢɟ ɨɛɪɚɬɧɵɟ ɫɜɹɡɢ (ɜ ɫɟɪɢɢ ɨɩɟ- ɪɚɬɨɪɨɜ ɩɨɫɥɟ ɤɥɸɱɟɜɨɝɨ ɫɥɨɜɚ LOGIC) ɡɚɩɪɟɳɚɸɬɫɹ. Ɍ.ɟ., ɩɟɪɟɦɟɧɧɵɟ, ɢɫ- ɩɨɥɶɡɭɟɦɵɟ ɜ ɥɨɝɢɱɟɫɤɢɯ ɜɵɪɚɠɟɧɢɹɯ ɞɨɥɠɧɵ ɛɵɬɶ ɡɚɪɚɧɟɟ ɢɡɜɟɫɬɧɵ, ɬ.ɟ. ɪɚɫɫɱɢɬɚɧɵ ɩɪɟɞɜɚɪɢɬɟɥɶɧɨ.

ȼ ɤɚɱɟɫɬɜɟ ɩɪɢɦɟɪɚ ɫɦ. ɨɩɪɟɞɟɥɟɧɢɟ ɩɨɥɧɨɝɨ ɫɭɦɦɚɬɨɪɚ 7483A ɜ ɛɢɛ- ɥɢɨɬɟɤɟ ɰɢɮɪɨɜɵɯ SPICE-ɩɨɞɫɯɟɦ DIG000.LIB.

13.4. Ƚɟɧɟɪɚɬɨɪɵ ɰɢɮɪɨɜɵɯ ɫɢɝɧɚɥɨɜ (Stimulus generators)

ɐɢɮɪɨɜɵɟ ɫɯɟɦɵ ɨɛɵɱɧɨ ɬɪɟɛɭɸɬ ɧɚɥɢɱɢɹ ɢɫɬɨɱɧɢɤɨɜ ɰɢɮɪɨɜɵɯ ɫɢɝɧɚ- ɥɨɜ ɞɥɹ ɦɨɞɟɥɢɪɨɜɚɧɢɹ ɪɚɛɨɬɵ ɭɫɬɪɨɣɫɬɜɚ ɢ ɟɝɨ ɬɟɫɬɢɪɨɜɚɧɢɹ. Ɍɚɤɢɟ ɢɫɬɨɱ- ɧɢɤɢ ɞɨɥɠɧɵ ɝɟɧɟɪɢɪɨɜɚɬɶ ɩɨɫɥɟɞɨɜɚɬɟɥɶɧɨɫɬɶ ɰɢɮɪɨɜɵɯ ɫɨɫɬɨɹɧɢɣ. Ƚɟɧɟ-

ɪɚɬɨɪɵ ɰɢɮɪɨɜɵɯ ɫɢɝɧɚɥɨɜ ɹɜɥɹɸɬɫɹ ɰɢɮɪɨɜɵɦɢ ɷɤɜɢɜɚɥɟɧɬɚɦɢ ɢɫɬɨɱɧɢɤɨɜ ɚɧɚɥɨɝɨɜɨɝɨ ɫɢɝɧɚɥɚ: SIN, PULSE, USER, Voltage Source, ɢ Current Source. ȼ Micro-Cap ɫɭɳɟɫɬɜɭɸɬ 2 ɬɢɩɚ ɬɚɤɢɯ ɝɟɧɟɪɚɬɨɪɨɜ: ɫɚɦɨɫɬɨɹɬɟɥɶɧɵɟ ɝɟɧɟɪɚɬɨ- ɪɵ ɰɢɮɪɨɜɵɯ ɫɢɝɧɚɥɨɜ (STIM) ɢ ɮɚɣɥɨɜɵɟ ɝɟɧɟɪɚɬɨɪɵ ɰɢɮɪɨɜɵɯ ɫɢɝɧɚɥɨɜ (FSTIM). STIM-ɝɟɧɟɪɚɬɨɪ ɢɫɩɨɥɶɡɭɟɬ ɤɨɦɚɧɞɧɵɣ ɹɡɵɤ ɞɥɹ ɫɨɡɞɚɧɢɹ ɰɢɮɪɨɜɨ- ɝɨ ɫɢɝɧɚɥɚ ɥɸɛɨɣ ɮɨɪɦɵ. FSTIM-ɝɟɧɟɪɚɬɨɪ ɞɥɹ ɫɨɡɞɚɧɢɹ ɰɢɮɪɨɜɨɝɨ ɫɢɝɧɚɥɚ ɫɱɢɬɵɜɚɟɬ ɞɚɧɧɵɟ ɢɡ ɜɧɟɲɧɟɝɨ ɮɚɣɥɚ, ɝɞɟ ɡɚɪɚɧɟɟ ɡɚɩɪɨɝɪɚɦɦɢɪɨɜɚɧɚ ɮɨɪ- ɦɚ ɷɬɨɝɨ ɫɢɝɧɚɥɚ. Ɋɚɫɫɦɚɬɪɢɜɚɟɦɵɟ ɤɨɦɩɨɧɟɧɬɵ ɧɟ ɢɦɟɸɬ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟ- ɥɢ, ɩɨɫɤɨɥɶɤɭ ɫɨɨɬɜɟɬɫɬɜɭɸɳɚɹ ɢɧɮɨɪɦɚɰɢɹ ɹɜɥɹɟɬɫɹ ɫɜɨɣɫɬɜɨɦ ɫɚɦɢɯ ɝɟɧɟ- ɪɢɪɭɟɦɵɯ ɫɢɝɧɚɥɨɜ.

13.4.1. Ƚɟɧɟɪɚɬɨɪɵ ɫɢɝɧɚɥɨɜ ɬɢɩɚ STIM

Ƚɟɧɟɪɚɬɨɪɵ STIM ɢɦɟɸɬ ɝɢɛɤɢɣ ɤɨɦɚɧɞɧɵɣ ɹɡɵɤ ɞɥɹ ɫɨɡɞɚɧɢɹ ɩɪɟɞɟɥɶɧɨ ɫɥɨɠɧɵɯ ɰɢɮɪɨɜɵɯ ɩɨɫɥɟɞɨɜɚɬɟɥɶɧɨɫɬɟɣ.

Ɏɨɪɦɚɬ SPICE

U<ɢɦɹ> STIM(<ɪɚɡɪɹɞɧɨɫɬɶ>,<ɮɨɪɦɚɬ ɦɚɫɫɢɜɚ>)

+<ɭɡɟɥ ɰɢɮɪɨɜɨɝɨ ɩɢɬɚɧɢɹ> <ɭɡɟɥ ɰɢɮɪɨɜɨɣ ɡɟɦɥɢ> <ɭɡɟɥ>* +<ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>]

+[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>] +[TIMESTEP=<ɜɪɟɦɟɧɧɨɣ ɲɚɝ>] <ɤɨɦɚɧɞɚ>*

Ɏɨɪɦɚɬ ɫɯɟɦ Micro-Cap

ɇɢɠɟ ɩɟɪɟɱɢɫɥɟɧɵ ɚɬɪɢɛɭɬɵ, ɫɩɟɰɢɮɢɱɧɵɟ ɞɥɹ STIM ɝɟɧɟɪɚɬɨɪɚ ɰɢɮɪɨ- ɜɵɯ ɫɢɝɧɚɥɨɜ.

xɬɪɢɛɭɬ FORMAT: <ɮɨɪɦɚɬ ɦɚɫɫɢɜɚ>

ɉɪɢɦɟɪ:

1111 ; ɱɢɫɥɨ, ɫɨɫɬɨɹɳɟɟ ɢɡ ɱɟɬɵɪɟɯ ɞɜɨɢɱɧɵɯ ɰɢɮɪ

xɬɪɢɛɭɬ COMMAND: <ɢɦɹ ɤɨɦɚɧɞɵ>

ɉɪɢɦɟɪ: BINARY1/6

xɬɪɢɛɭɬ TIMESTEP: [<ɜɪɟɦɟɧɧɨɣ ɲɚɝ>]

ɉɪɢɦɟɪ: 10ns

Ɉɩɪɟɞɟɥɟɧɢɹ

<ɪɚɡɪɹɞɧɨɫɬɶ> — ɜ SPICE-ɮɚɣɥɟ ɷɬɨɬ ɚɬɪɢɛɭɬ ɨɛɨɡɧɚɱɚɟɬ ɱɢɫɥɨ ɜɵɯɨɞ- ɧɵɯ ɫɢɝɧɚɥɨɜ ɝɟɧɟɪɚɬɨɪɚ, ɩɨ ɫɭɬɢ ɷɬɨ ɪɚɡɪɹɞɧɨɫɬɶ ɜ ɛɢɬɚɯ. Ⱦɥɹ ɫɯɟɦ Micro-Cap ɪɚɡɪɹɞɧɨɫɬɶ ɝɟɧɟɪɚɬɨɪɚ ɭɫɬɚɧɚɜɥɢɜɚɟɬɫɹ, ɤɨɝɞɚ ɝɟɧɟɪɚɬɨɪ ɩɨɦɟɳɚɟɬɫɹ ɜ ɛɢɛ- ɥɢɨɬɟɤɭ ɤɨɦɩɨɧɟɧɬɨɜ, ɩɨɷɬɨɦɭ ɩɪɨɫɬɨɣ ɜɵɛɨɪ ɝɟɧɟɪɚɬɨɪɚ ɬɢɩɚ STIM ɢɡ ɛɢɛɥɢɨ- ɬɟɤɢ ɫɪɚɡɭ ɡɚɩɨɥɧɹɟɬ ɷɬɨɬ ɚɬɪɢɛɭɬ.

<ɮɨɪɦɚɬ ɦɚɫɫɢɜɚ>. ɋɬɪɨɤɚ <ɤɨɦɚɧɞɚ> ɢɫɩɨɥɶɡɭɟɬ ɩɨɥɟ <ɡɧɚɱɟɧɢɟ> ɞɥɹ ɨɩɢɫɚɧɢɹ ɜɵɯɨɞɧɵɯ ɫɨɫɬɨɹɧɢɣ ɝɟɧɟɪɚɬɨɪɚ (ɫɦ. ɧɢɠɟ ɮɨɪɦɚɬ <ɤɨɦɚɧɞɵ>).