Микросхемотехника / amelina_m_a_amelin_s_a_programma_shemotehnicheskogo_modeliro

Ɍɚɤɠɟ ɜ ɫɨɫɬɚɜ ɛɢɛɥɢɨɬɟɤɢ ɩɪɢɦɢɬɢɜɨɜ ɜɯɨɞɹɬ ɬɪɢɝɝɟɪɵ, ɩɟɪɟɤɥɸɱɚɸ- ɳɢɟɫɹ ɩɨ ɭɪɨɜɧɸ ɫɢɝɧɚɥɚ ɧɚ ɫɢɧɯɪɨɜɯɨɞɟ, ɢɥɢ ɬɚɤ ɧɚɡɵɜɚɟɦɵɟ ɡɚɳɺɥɤɢ (latches). ɗɬɨ ɫɢɧɯɪɨɧɧɵɣ RS-ɬɪɢɝɝɟɪ (SRFF), ɢ D-ɬɪɢɝɝɟɪ-ɡɚɳɟɥɤɚ (DLTCH). ȼɵɯɨɞɵ ɷɬɢɯ ɬɪɢɝɝɟɪɨɜ ɭɫɬɚɧɚɜɥɢɜɚɸɬɫɹ ɜ ɫɨɨɬɜɟɬɫɬɜɢɢ ɫ ɜɯɨɞɧɵɦɢ ɢɧɮɨɪ- ɦɚɰɢɨɧɧɵɦɢ ɫɢɝɧɚɥɚɦɢ, ɜ ɬɟɱɟɧɢɟ ɜɫɟɝɨ ɜɪɟɦɟɧɢ ɩɪɢɫɭɬɫɬɜɢɹ ɚɤɬɢɜɧɨɝɨ ɭɪɨɜɧɹ (ɜɵɫɨɤɨɝɨ) ɧɚ ɪɚɡɪɟɲɚɸɳɟɦ ɜɯɨɞɟ GATE ɢ ɧɟ ɦɟɧɹɸɬ ɫɜɨɟɝɨ ɫɨɫɬɨɹ- ɧɢɹ ɩɪɢ ɧɢɡɤɨɦ ɭɪɨɜɧɟ ɫɢɝɧɚɥɚ ɧɚ ɞɚɧɧɨɦ ɜɯɨɞɟ. ɥɝɨɪɢɬɦ ɮɭɧɤɰɢɨɧɢɪɨɜɚ- ɧɢɹ ɷɬɢɯ ɬɪɢɝɝɟɪɨɜ ɩɪɢɜɟɞɟɧ ɜ ɬɚɛɥ. 13.10, 13.11. ȼ ɧɢɯ ɢɦɹ ɜɵɯɨɞɚ ɬɪɢɝɝɟɪɚ ɫɨ ɲɬɪɢɯɨɦ ɨɛɨɡɧɚɱɚɟɬ ɟɝɨ ɩɪɟɞɵɞɭɳɟɟ ɫɨɫɬɨɹɧɢɟ.

Ɍ ɚ ɛ ɥ ɢ ɰ ɚ 1 3 . 1 0 . Ɍɚɛɥɢɰɚ ɢɫɬɢɧɧɨɫɬɢ ɬɪɢɝɝɟɪɚ SRFF

Ɍ ɚ ɛ ɥ ɢ ɰ ɚ 1 3 . 1 1 . Ɍɚɛɥɢɰɚ ɢɫɬɢɧɧɨɫɬɢ ɬɪɢɝɝɟɪɚ LATCH

ɇɚɱɚɥɶɧɚɹ ɭɫɬɚɧɨɜɤɚ ɬɪɢɝɝɟɪɨɜ. Ɍɪɢɝɝɟɪɵ ɫ ɞɢɧɚɦɢɱɟɫɤɢɦ ɫɢɧɯɪɨɜɯɨ- ɞɨɦ ɦɨɝɭɬ ɛɵɬɶ ɭɫɬɚɧɨɜɥɟɧɵ ɜ ɧɟɨɛɯɨɞɢɦɨɟ ɧɚɱɚɥɶɧɨɟ ɫɨɫɬɨɹɧɢɟ ɫɨɨɬɜɟɬɫɬ- ɜɭɸɳɟɣ ɭɫɬɚɧɨɜɤɨɣ ɩɚɪɚɦɟɬɪɚ DIGINITSTATE ɜ ɨɤɧɟ Global Settings. Ⱦɥɹ ɤɨɧ- ɤɪɟɬɧɨɣ ɫɯɟɦɵ ɷɬɨ ɦɨɠɧɨ ɫɞɟɥɚɬɶ ɫ ɩɨɦɨɳɶɸ ɞɢɪɟɤɬɢɜɵ .OPTIONS.

ɇɟɨɩɪɟɞɟɥɟɧɧɵɟ X ɭɪɨɜɧɢ ɧɚ ɜɯɨɞɚɯ ɩɪɟɞɭɫɬɚɧɨɜɤɢ. ɇɟɨɩɪɟɞɟɥɟɧ-

ɧɵɟ ɫɨɫɬɨɹɧɢɹ X ɧɟ ɪɚɫɩɪɨɫɬɪɚɧɹɸɬɫɹ ɧɚ ɜɵɯɨɞ, ɟɫɥɢ ɥɸɛɨɟ ɫɨɫɬɨɹɧɢɟ ɷɬɨɝɨ ɜɯɨɞɚ ɧɟ ɦɨɠɟɬ ɩɨɜɥɢɹɬɶ ɧɚ ɫɨɫɬɨɹɧɢɟ ɬɪɢɝɝɟɪɚ. ɇɚɩɪɢɦɟɪ, ɟɫɥɢ clearbar=X ɢ Q=0, ɬɨ ɜɵɯɨɞ Q ɨɫɬɚɧɟɬɫɹ ɜ ɧɢɡɤɨɦ ɫɨɫɬɨɹɧɢɢ, ɩɨɫɤɨɥɶɤɭ ɥɸɛɵɟ ɜɨɡɦɨɠɧɵɟ ɭɪɨɜɧɢ ɧɚ ɜɯɨɞɟ ɫɛɪɨɫɚ (clearbar=0 ɢ clearbar=1) ɧɟ ɢɡɦɟɧɹɬ ɧɢɡɤɢɣ ɭɪɨɜɟɧɶ ɜɵɯɨɞɚ Q=0.

ȿɫɥɢ ɧɟɨɩɪɟɞɟɥɟɧɧɵɣ ɭɪɨɜɟɧɶ X ɩɨɫɬɭɩɚɟɬ ɧɚ ɜɯɨɞ, ɤɨɬɨɪɵɣ ɫɩɨɫɨɛɟɧ ɩɨɜɥɢɹɬɶ ɧɚ ɫɨɫɬɨɹɧɢɟ ɬɪɢɝɝɟɪɚ, ɬɨ ɧɚ ɜɵɯɨɞɟ ɬɪɢɝɝɟɪɚ ɩɨɹɜɥɹɟɬɫɹ ɧɟɨɩɪɟ-

ɞɟɥɟɧɧɨɟ ɫɨɫɬɨɹɧɢɟ. ɇɚɩɪɢɦɟɪ, ɟɫɥɢ clearbar=X ɢ Q=1, ɬɨ Q ɢɡɦɟɧɢɬ ɫɜɨɟ ɫɨɫɬɨɹɧɢɟ ɧɚ ɧɟɨɩɪɟɞɟɥɟɧɧɨɟ X, ɩɨɫɤɨɥɶɤɭ ɞɜɚ ɜɨɡɦɨɠɧɵɯ ɭɪɨɜɧɹ ɧɚ ɜɯɨɞɟ ɫɛɪɨɫɚ (clearbar=0 ɢ clearbar=1) ɜɵɡɵɜɚɸɬ ɪɚɡɧɵɟ ɜɵɯɨɞɧɵɟ ɫɨɫɬɨɹɧɢɹ Q

(Q=0 ɢ Q=1).

ɇɚɪɭɲɟɧɢɟ ɜɪɟɦɟɧɧɵɯ ɨɝɪɚɧɢɱɟɧɢɣ. ȼɪɟɦɟɧɧɵɟ ɨɝɪɚɧɢɱɟɧɢɹ, ɩɪɢɜɟ-

ɞɟɧɧɵɟ ɜ ɬɚɛɥɢɰɚɯ 13.12–13.13 ɩɪɨɜɟɪɹɸɬɫɹ ɥɢɲɶ ɜ ɬɨɦ ɫɥɭɱɚɟ, ɟɫɥɢ ɢɯ ɜɟ- ɥɢɱɢɧɵ ɨɬɥɢɱɧɵ ɨɬ ɧɭɥɹ. ȿɫɥɢ ɜɪɟɦɟɧɧɵɟ ɨɝɪɚɧɢɱɟɧɢɹ ɧɚɪɭɲɚɸɬɫɹ, MicroCap ɫɨɡɞɚɟɬ ɩɪɟɞɭɩɪɟɠɞɚɸɳɟɟ ɫɨɨɛɳɟɧɢɟ ɜ ɨɤɧɟ ɱɢɫɥɟɧɧɨɝɨ ɜɵɜɨɞɚ Numeric Output ɢ ɜ ɬɟɤɫɬɨɜɨɦ ɮɚɣɥɟ <ɂɦɹ_ɫɯɟɦɵ>.TNO.

Ɇɚɫɫɢɜɵ ɬɪɢɝɝɟɪɨɜ. Ɇɚɫɫɢɜɵ ɬɪɢɝɝɟɪɨɜ ɞɨɫɬɭɩɧɵ ɬɨɥɶɤɨ ɱɟɪɟɡ SPICE- ɬɟɤɫɬ, ɢɥɢ ɛɢɛɥɢɨɬɟɤɭ SPICE-ɩɨɞɫɯɟɦ. Ⱦɥɹ ɦɚɫɫɢɜɨɜ ɬɪɢɝɝɟɪɨɜ Flip-Flops ɬɚɤ- ɬɨɜɵɣ ɜɯɨɞ (CLOCK) ɢ ɜɯɨɞɵ ɩɪɟɞɭɫɬɚɧɨɜɤɢ-ɫɛɪɨɫɚ (PRESETBAR, CLEARBAR) ɹɜɥɹɸɬɫɹ ɨɛɳɢɦɢ ɞɥɹ ɜɫɟɯ ɷɥɟɦɟɧɬɨɜ ɦɚɫɫɢɜɚ. Ⱦɥɹ ɦɚɫɫɢɜɨɜ ɬɪɢɝɝɟɪɨɜ-ɡɚɳɟɥɨɤ (Latches) ɜɯɨɞ ɪɚɡɪɟɲɟɧɢɹ (GATE) ɢ ɜɯɨɞɵ ɩɪɟɞɭɫɬɚɧɨɜɤɢ- ɫɛɪɨɫɚ (PRESETBAR, CLEARBAR) ɹɜɥɹɸɬɫɹ ɨɛɳɢɦɢ ɞɥɹ ɜɫɟɯ ɷɥɟɦɟɧɬɨɜ ɦɚɫɫɢɜɚ.

Ɍ ɚ ɛ ɥ ɢ ɰ ɚ 1 3 . 1 2 . ɉɚɪɚɦɟɬɪɵ ɦɨɞɟɥɢ ɬɪɢɝɝɟɪɨɜ, ɩɟɪɟɤɥɸɱɚɟɦɵɯ ɮɪɨɧɬɨɦ

ɫɢɧɯɪɨɫɢɝɧɚɥɚ (JKFF, DFF), ɫ

TPPCQLHMN Ɇɢɧɢɦɚɥɶɧɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 0 ɜ 1 ɩɨ ɜɯɨɞɚɦ PREB/CLRB

TPPCQLHTY Ɍɢɩɨɜɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 0 ɜ 1 ɩɨ ɜɯɨɞɚɦ PREB/CLRB

TPPCQLHMX Ɇɚɤɫɢɦɚɥɶɧɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 0 ɜ 1 ɩɨ ɜɯɨɞɚɦ PREB/CLRB

TPPCQHLMN Ɇɢɧɢɦɚɥɶɧɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 1 ɜ 0 ɩɨ ɜɯɨɞɚɦ PREB/CLRB

TPPCQHLTY Ɍɢɩɨɜɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 1 ɜ 0 ɩɨ ɜɯɨɞɚɦ PREB/CLRB

TPPCQHLMX Ɇɚɤɫɢɦɚɥɶɧɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 1 ɜ 0 ɩɨ ɜɯɨɞɚɦ PREB/CLRB

TWPCLMN Ɇɢɧɢɦɚɥɶɧɚɹ ɞɥɢɬɟɥɶɧɨɫɬɶ ɧɢɡɤɨɝɨ ɭɪɨɜɧɹ ɧɚ ɜɯɨɞɚɯ PREB/CLRB

TWPCLTY Ɍɢɩɨɜɚɹ ɞɥɢɬɟɥɶɧɨɫɬɶ ɧɢɡɤɨɝɨ ɭɪɨɜɧɹ ɧɚ ɜɯɨɞɚɯ PREB/CLRB

TWPCLMX Ɇɚɤɫɢɦɚɥɶɧɚɹ ɞɥɢɬɟɥɶɧɨɫɬɶ ɧɢɡɤɨɝɨ ɭɪɨɜɧɹ ɧɚ ɜɯɨɞɚɯ PREB/CLRB

TPGQLHMN Ɇɢɧɢɦɚɥɶɧɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 0 ɜ 1 ɩɨ ɫɢɧɯɪɨɜɯɨɞɭ GATE

TPGQLHTY Ɍɢɩɨɜɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 0 ɜ 1 ɩɨ ɫɢɧɯɪɨɜɯɨɞɭ GATE

TPGQLHMX Ɇɚɤɫɢɦɚɥɶɧɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 0 ɜ 1 ɩɨ ɫɢɧɯɪɨɜɯɨɞɭ GATE

TPGQHLMN Ɇɢɧɢɦɚɥɶɧɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 1 ɜ 0 ɩɨ ɫɢɧɯɪɨɜɯɨɞɭ GATE

TPGQHLTY Ɍɢɩɨɜɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 1 ɜ 0 ɩɨ ɫɢɧɯɪɨɜɯɨɞɭ GATE

TPGQHLMX Ɇɚɤɫɢɦɚɥɶɧɚɹ ɡɚɞɟɪɠɤɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɢɡ 1 ɜ 0 ɩɨ ɫɢɧɯɪɨɜɯɨɞɭ GATE

Ɏɨɪɦɚɬ SPICE

U<ɢɦɹ> JKFF(<ɤɨɥɢɱɟɫɬɜɨ ɬɪɢɝɝɟɪɨɜ flip-flops >) +<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ> +<ɜɯɨɞ presetbar> <ɜɯɨɞ clearbar> <ɜɯɨɞ clockbar> +<ɩɟɪɜɵɣ ɜɯɨɞ J>...<ɩɨɫɥɟɞɧɢɣ ɜɯɨɞ J>

+<ɩɟɪɜɵɣ ɜɯɨɞ K>...<ɩɨɫɥɟɞɧɢɣ ɜɯɨɞ K> +<ɩɟɪɜɵɣ ɜɵɯɨɞ Q>...<ɩɨɫɥɟɞɧɢɣ ɜɵɯɨɞ Q> +<ɩɟɪɜɵɣ ɜɵɯɨɞ Qbar>...<ɩɨɫɥɟɞɧɢɣ ɜɵɯɨɞ Qbar>

+<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ> +[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>] +[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>]

U<ɢɦɹ> DFF(<ɤɨɥɢɱɟɫɬɜɨ ɬɪɢɝɝɟɪɨɜ flip-flops>) +<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ> +<ɜɯɨɞ presetbar> <ɜɯɨɞ clearbar> <ɜɯɨɞ clock> +<ɩɟɪɜɵɣ ɜɯɨɞ D>...<ɩɨɫɥɟɞɧɢɣ ɜɯɨɞ D>

+<ɩɟɪɜɵɣ ɜɵɯɨɞ Q>...<ɩɨɫɥɟɞɧɢɣ ɜɵɯɨɞ Q> +<ɩɟɪɜɵɣ ɜɵɯɨɞ Qbar>...<ɩɨɫɥɟɞɧɢɣ ɜɵɯɨɞ Qbar>

+<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ> +[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>] +[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>]

U<ɢɦɹ> SRFF(<ɤɨɥɢɱɟɫɬɜɨ ɬɪɢɝɝɟɪɨɜ latches>) +<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ> +<ɜɯɨɞ presetbar> <ɜɯɨɞ clearbar> <ɜɯɨɞ gate> +<ɩɟɪɜɵɣ ɜɯɨɞ S>...<ɩɨɫɥɟɞɧɢɣ ɜɯɨɞ S>

+<ɩɟɪɜɵɣ ɜɯɨɞ R>...<ɩɨɫɥɟɞɧɢɣ ɜɯɨɞ R> +<ɩɟɪɜɵɣ ɜɵɯɨɞ Q>...<ɩɨɫɥɟɞɧɢɣ ɜɵɯɨɞ Q> +<ɩɟɪɜɵɣ ɜɵɯɨɞ Qbar>...<ɩɨɫɥɟɞɧɢɣ ɜɵɯɨɞ Qbar>

+<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ> +[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>] +[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>]

U<ɢɦɹ> DLTCH(<ɤɨɥɢɱɟɫɬɜɨ ɬɪɢɝɝɟɪɨɜ latches>) +<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ> +<ɜɯɨɞ presetbar> <ɜɯɨɞ clearbar> <ɜɯɨɞ gate> +<ɩɟɪɜɵɣ ɜɯɨɞ D>...<ɩɨɫɥɟɞɧɢɣ ɜɯɨɞ D>

+<ɩɟɪɜɵɣ ɜɵɯɨɞ Q>...<ɩɨɫɥɟɞɧɢɣ ɜɵɯɨɞ Q> +<ɩɟɪɜɵɣ ɜɵɯɨɞ Qbar>...<ɩɨɫɥɟɞɧɢɣ ɜɵɯɨɞ Qbar>

+<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ> +[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>] +[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>]

ɉɪɢɦɟɪɵ:

U1 JKFF(2) $G_DPWR $G_DGND

+ PREBAR CLRBAR CLKBAR J1 J2 K1 K2 Q1 Q2 Q1BAR Q2BAR +D0_EFF IO_STD IO_LEVEL=1

U4 DFF(1) $G_DPWR $G_DGND

+PREB CLRB CLK DIN Q QBAR DLY_DFF IO_ACT

U1 SRFF(2) $G_DPWR $G_DGND

+ PREBAR CLRBAR CLK S1 S2 R1 R2 Q1 Q2 Q1BAR Q2BAR +D0_SRFF IO_STD IO_LEVEL=1

U4 DLTCH(1) $G_DPWR $G_DGND

+PREB CLRB GATE D1 Q QBAR D_DLTCH IO_ALS’

Ɏɨɪɦɚɬ ɫɯɟɦ Micro-Cap

xɬɪɢɛɭɬ PART: <ɢɦɹ> ɉɪɢɦɟɪ: U10

xɬɪɢɛɭɬ TIMING MODEL: <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ>

ɉɪɢɦɟɪ: 74XX

xɬɪɢɛɭɬ I/O MODEL: <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

ɉɪɢɦɟɪ: IO_STD

xɬɪɢɛɭɬ MNTYMXDLY: <ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>

ɉɪɢɦɟɪ: 1

xɬɪɢɛɭɬ IO_LEVEL: <ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>

ɉɪɢɦɟɪ: 0

xɬɪɢɛɭɬ POWER NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ>

ɉɪɢɦɟɪ: $G_DPWR

xɬɪɢɛɭɬ GROUND NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ>

ɉɪɢɦɟɪ: $G_DGND

Ɏɨɪɦɚɬ ɞɢɪɟɤɬɢɜɵ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ (Timing Model)

Ⱦɥɹ ɬɪɢɝɝɟɪɨɜ, ɩɟɪɟɤɥɸɱɚɟɦɵɯ ɮɪɨɧɬɨɦ (JKFF, DFF):

.MODEL <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> UEFF ([ɩɚɪɚɦɟɬɪɵ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ])

Ⱦɥɹ ɬɪɢɝɝɟɪɨɜ, ɩɟɪɟɤɥɸɱɚɟɦɵɯ ɭɪɨɜɧɟɦ (SRFF, DLTCH):

.MODEL <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> UGFF ([ɩɚɪɚɦɟɬɪɵ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ])

ɉɪɢɦɟɪɵ:

.MODEL JKDLY UEFF (tppcqlhty=10ns tppcqlhmx=25ns tpclkqlhty=12ns +twpclty=15ns tsudclkty=4ns)

.MODEL SR1 UGFF (tppcqlhty=10ns tppcqlhmx=25ns tpgqlhty=12ns +twpclty=15ns tsudgty=4ns)

13.2.6. ɉɨɞɬɹɝɢɜɚɸɳɢɟ ɪɟɡɢɫɬɨɪɵ Pullup ɢ Pulldown

ɗɬɢ ɤɨɦɩɨɧɟɧɬɵ ɢɫɩɨɥɶɡɭɸɬɫɹ ɞɥɹ ɡɚɞɚɧɢɹ ɥɨɝɢɱɟɫɤɢɯ ɭɪɨɜɧɟɣ ɫ ɨɩɪɟ- ɞɟɥɟɧɧɨɣ ɧɚɝɪɭɡɨɱɧɨɣ ɫɩɨɫɨɛɧɨɫɬɶɸ. ȼɵɯɨɞɵ ɞɚɧɧɵɯ ɤɨɦɩɨɧɟɧɬɨɜ ɨɛɟɫɩɟɱɢ- ɜɚɸɬ ɫɥɟɞɭɸɳɢɟ ɰɢɮɪɨɜɵɟ ɭɪɨɜɧɢ:

ɋɥɟɞɭɟɬ ɨɬɦɟɬɢɬɶ, ɱɬɨ ɷɬɢ ɤɨɦɩɨɧɟɧɬɵ – ɱɢɫɬɨ ɰɢɮɪɨɜɵɟ ɭɫɬɪɨɣɫɬɜɚ (ɚ ɧɟ ɚɧɚɥɨɝɨɜɵɟ). Ɉɫɧɨɜɧɚɹ ɰɟɥɶ ɢɯ ɢɫɩɨɥɶɡɨɜɚɧɢɹ – ɨɛɟɫɩɟɱɟɧɢɟ ɥɨɝɢɱɟɫɤɨɣ

ɟɞɢɧɢɰɵ ɞɥɹ ɜɵɯɨɞɨɜ ɫ ɨɬɤɪɵɬɵɦ ɤɨɥɥɟɤɬɨɪɨɦ ɢ ɨɛɴɟɞɢɧɟɧɢɹ ɷɬɢɯ ɜɵɯɨɞɨɜ ɩɨ ɫɯɟɦɟ «ɦɨɧɬɚɠɧɨɟ ɂ».

Ʉɨɦɩɨɧɟɧɬɵ PULLUP ɢ PULLDN ɧɟ ɢɫɩɨɥɶɡɭɸɬ ɜɪɟɦɟɧɧɭɸ ɦɨɞɟɥɶ, ɩɨ- ɫɤɨɥɶɤɭ ɧɟ ɜɧɨɫɹɬ ɡɚɞɟɪɠɤɭ ɜ ɪɚɫɩɪɨɫɬɪɚɧɟɧɢɟ ɫɢɝɧɚɥɚ. Ɉɞɧɚɤɨ ɨɧɢ ɧɭɠɞɚ- ɸɬɫɹ ɜ ɨɩɪɟɞɟɥɟɧɢɢ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ, ɩɨɫɤɨɥɶɤɭ ɩɨ ɫɭɬɢ ɨɫɬɚɸɬɫɹ ɰɢɮ- ɪɨɜɵɦɢ ɩɪɢɛɨɪɚɦɢ.

Ɏɨɪɦɚɬ SPICE

U<ɢɦɹ> <ɬɢɩ ɪɟɡɢɫɬɨɪɚ>(<ɤɨɥɢɱɟɫɬɜɨ ɪɟɡɢɫɬɨɪɨɜ>) +<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ> +<ɜɵɯɨɞ>* +<ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

+[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>]

<ɬɢɩ ɪɟɡɢɫɬɨɪɚ> ɦɨɠɟɬ ɛɵɬɶ ɞɜɭɯ ɜɢɞɨɜ:

PULLUP — ɦɚɫɫɢɜ ɰɢɮɪɨɜɵɯ ɪɟɡɢɫɬɨɪɨɜ, ɩɨɞɬɹɝɢɜɚɸɳɢɯ ɤ ɜɵɫɨɤɨɦɭ ɭɪɨɜɧɸ.

PULLDN — ɦɚɫɫɢɜ ɰɢɮɪɨɜɵɯ ɪɟɡɢɫɬɨɪɨɜ, ɩɨɞɬɹɝɢɜɚɸɳɢɯ ɤ ɧɢɡɤɨɦɭ ɭɪɨɜɧɸ.

<ɤɨɥɢɱɟɫɬɜɨ ɪɟɡɢɫɬɨɪɨɜ> — ɤɨɥɢɱɟɫɬɜɨ ɪɟɡɢɫɬɨɪɨɜ ɜ ɦɚɬɪɢɰɟ.

ɉɪɢɦɟɪ:

U1 PULLUP(8) $G_DPWR $G_DGND A1 A2 A3 A4 A5 A6 A7 A8 IO_STD

Ɏɨɪɦɚɬ ɫɯɟɦ Micro-Cap

xɬɪɢɛɭɬ PART: <ɢɦɹ>

xɬɪɢɛɭɬ I/O MODEL: <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

xɬɪɢɛɭɬ IO_LEVEL: <ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>

xɬɪɢɛɭɬ POWER NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ>

xɬɪɢɛɭɬ GROUND NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ>

13.2.7. ɐɢɮɪɨɜɚɹ ɛɟɡɵɧɟɪɰɢɨɧɧɚɹ ɥɢɧɢɹ ɡɚɞɟɪɠɤɢ Dlyline

ɗɬɨɬ ɤɨɦɩɨɧɟɧɬ ɡɚɞɟɪɠɢɜɚɟɬ ɰɢɮɪɨɜɨɣ ɫɢɝɧɚɥ ɧɚ ɩɨɫɬɨɹɧɧɭɸ ɜɟɥɢɱɢɧɭ ɜ ɫɨɨɬɜɟɬɫɬɜɢɢ ɫ ɩɚɪɚɦɟɬɪɚɦɢ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ (ɬɚɛɥ. 13.14). ȼ ɨɬɥɢɱɢɟ ɨɬ

ɞɪɭɝɢɯ ɰɢɮɪɨɜɵɯ ɤɨɦɩɨɧɟɧɬɨɜ ɨɧ ɧɟ ɨɛɥɚɞɚɟɬ ɢɧɟɪɰɢɨɧɧɵɦ ɚɧɧɭɥɢɪɨɜɚɧɢɟɦ ɫɢɝɧɚɥɚ (Inertial Cancellation). ɑɟɪɟɡ ɧɟɝɨ ɫ ɡɚɞɚɧɧɨɣ ɡɚɞɟɪɠɤɨɣ ɩɪɨɯɨɞɹɬ ɫɤɨɥɶ ɭɝɨɞɧɨ ɤɨɪɨɬɤɢɟ ɢɦɩɭɥɶɫɵ.

Ɏɨɪɦɚɬ SPICE

U<ɢɦɹ> DLYLINE

+<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ> +<ɜɯɨɞ> <ɜɵɯɨɞ> +<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

+[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>] +[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>]

ɉɪɢɦɟɪ:

U1 DLYLINE $G_DPWR $G_DGND IN OUT DMOD IO1

Ɏɨɪɦɚɬ ɫɯɟɦ Micro-Cap

xɬɪɢɛɭɬ PART: <ɢɦɹ>

xɬɪɢɛɭɬ TIMING MODEL: <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ>

xɬɪɢɛɭɬ I/O MODEL: <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

xɬɪɢɛɭɬ MNTYMXDLY: <ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>

xɬɪɢɛɭɬ IO_LEVEL: <ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>

xɬɪɢɛɭɬ POWER NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ>

xɬɪɢɛɭɬ GROUND NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ>

Ɍ ɚ ɛ ɥ ɢ ɰ ɚ 1 3 . 1 4 . ɉɚɪɚɦɟɬɪɵ ɦɨɞɟɥɢ ɰɢɮɪɨɜɨɣ ɥɢɧɢɢ ɡɚɞɟɪɠɤɢ, ɫ

13.2.8. ɉɪɨɝɪɚɦɦɢɪɭɟɦɵɟ ɥɨɝɢɱɟɫɤɢɟ ɦɚɬɪɢɰɵ

ɉɪɨɝɪɚɦɦɢɪɭɟɦɵɟ ɥɨɝɢɱɟɫɤɢɟ ɦɚɬɪɢɰɵ ɜɜɟɞɟɧɵ ɜ ɩɪɨɝɪɚɦɦɭ ɞɥɹ ɦɨɞɟ- ɥɢɪɨɜɚɧɢɹ ɲɢɪɨɤɨɝɨ ɤɥɚɫɫɚ ɭɫɬɪɨɣɫɬɜ ɫ ɩɪɨɝɪɚɦɦɢɪɭɟɦɨɣ ɥɨɝɢɤɨɣ. Ɇɨɞɟɥɶ ɜɵɩɨɥɧɟɧɚ ɫ ɜɨɡɦɨɠɧɨɫɬɶɸ ɨɩɪɟɞɟɥɟɧɢɹ ɩɨɥɶɡɨɜɚɬɟɥɟɦ ɤɨɥɢɱɟɫɬɜɚ ɜɯɨɞɨɜ, ɜɢɡɭɚɥɢɡɚɰɢɢ ɡɚɩɪɨɝɪɚɦɦɢɪɨɜɚɧɧɵɯ ɫɬɨɥɛɰɨɜ, ɨɩɪɟɞɟɥɟɧɢɹ ɤɨɥɢɱɟɫɬɜɚ ɜɵ-

ɯɨɞɨɜ, ɤɨɬɨɪɵɟ ɮɨɪɦɢɪɭɸɬ ɪɹɞɵ. Ʉɚɠɞɵɣ ɜɵɯɨɞ (ɪɹɞ) — ɷɬɨ ɜɟɧɬɢɥɶ, ɜɯɨɞɵ ɤɨɬɨɪɨɝɨ ɜɵɛɢɪɚɸɬɫɹ ɜɯɨɞɧɵɦɢ ɫɢɝɧɚɥɚɦɢ (ɫɬɨɥɛɰɚɦɢ), ɤɚɤ ɩɨɤɚɡɚɧɨ ɧɚ ɪɢɫ. 13.13. ɍɫɬɪɨɣɫɬɜɨ ɩɪɨɝɪɚɦɦɢɪɭɟɬɫɹ ɜɵɛɨɪɨɦ ɜɯɨɞɨɜ, ɤɨɬɨɪɵɟ ɛɭɞɭɬ ɹɜ- ɥɹɬɶɫɹ ɱɚɫɬɶɸ ɜɵɯɨɞɧɨɝɨ ɜɟɧɬɢɥɹ. Ɍɢɩ ɜɵɯɨɞɧɨɝɨ ɜɟɧɬɢɥɹ ɨɩɪɟɞɟɥɹɟɬɫɹ ɬɢ- ɩɨɦ ɩɪɨɝɪɚɦɦɢɪɭɟɦɨɣ ɦɚɬɪɢɰɵ. Ɇɚɬɪɢɰɚ PLNAND ɢɦɟɟɬ ɜɵɯɨɞɧɵɟ ɜɟɧɬɢɥɢ ɂ-ɇȿ (NAND), PLOR — ɂɅɂ (OR). Ʉɨɦɩɨɧɟɧɬ PLA ɨɛɟɫɩɟɱɢɜɚɟɬ ɩɪɨɝɪɚɦɦɢ- ɪɭɟɦɭɸ ɫɟɪɞɰɟɜɢɧɭ ɞɥɹ ɦɨɞɟɥɢɪɨɜɚɧɢɹ ɪɟɚɥɶɧɵɯ ɜɵɩɭɫɤɚɟɦɵɯ ɩɪɨɦɵɲɥɟɧ- ɧɨɫɬɶɸ ɩɪɢɛɨɪɨɜ ɫ ɩɪɨɝɪɚɦɦɢɪɭɟɦɨɣ ɥɨɝɢɤɨɣ.

Ɋɢɫ. 13.13. ɉɪɨɝɪɚɦɦɢɪɭɟɦɚɹ ɥɨɝɢɱɟɫɤɚɹ ɦɚɬɪɢɰɚ PLANDC 3X4

ɋɭɳɟɫɬɜɭɸɬ 2 ɫɩɨɫɨɛɚ ɩɪɨɝɪɚɦɦɢɪɨɜɚɧɢɹ ɦɚɬɪɢɰ. ɉɟɪɜɵɣ — ɷɬɨ ɡɚɩɢɫɶ ɞɚɧɧɵɯ ɜ ɮɚɣɥ ɮɨɪɦɚɬɚ JEDEC. Ɍɚɤɢɟ ɮɚɣɥɵ ɨɛɵɱɧɨ ɹɜɥɹɸɬɫɹ ɩɟɪɜɢɱɧɵɦ

ɩɪɨɞɭɤɬɨɦ ɫɢɫɬɟɦɵ ɩɪɨɟɤɬɢɪɨɜɚɧɢɹ ɭɫɬɪɨɣɫɬɜ ɧɚ ɨɫɧɨɜɟ ɩɪɨɝɪɚɦɦɢɪɭɟɦɵɯ ɥɨɝɢɱɟɫɤɢɯ ɦɚɬɪɢɰ. ȼɬɨɪɨɣ ɫɩɨɫɨɛ ɫɨɫɬɨɢɬ ɜ ɧɟɩɨɫɪɟɞɫɬɜɟɧɧɨɣ ɡɚɩɢɫɢ ɞɚɧ- ɧɵɯ ɜ ɤɨɦɚɧɞɧɭɸ ɫɬɪɨɤɭ SPICE-ɬɟɤɫɬɚ ɞɥɹ ɫɯɟɦɵ.

Ɏɨɪɦɚɬ SPICE

U<ɢɦɹ> <ɬɢɩ PLD>(<ɤɨɥ. ɜɯɨɞɨɜ>,<ɤɨɥ. ɜɵɯɨɞɨɜ>) +<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ> +<ɜɯɨɞɧɨɣ ɭɡɟɥ>* <ɜɵɯɨɞɧɨɣ ɭɡɟɥ>* +<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

+[FILE=<"ɤɨɧɫɬɚɧɬɚ ɢɦɟɧɢ ɮɚɣɥɚ" | |ɜɵɪɚɠɟɧɢɟ ɢɦɟɧɢ ɮɚɣɥɚ|>] +[DATA=<ɤɨɧɫɬɚɧɬɚ ɞɚɧɧɵɯ>|<ɩɪɢɡɧɚɤ ɫɢɫɬɟɦɵ ɫɱɢɫɥɟɧɢɹ>$<ɬɚɛɥɢɰɚ

ɞɚɧɧɵɯ>$]

+[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>] +[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>]

Ɏɨɪɦɚɬ ɫɯɟɦ Micro-Cap

xɬɪɢɛɭɬ PART: <ɢɦɹ>

xɬɪɢɛɭɬ TIMING MODEL: <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ>

xɬɪɢɛɭɬ I/O MODEL: <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

xɬɪɢɛɭɬ FILE: <"ɤɨɧɫɬɚɧɬɚ ɢɦɟɧɢ ɮɚɣɥɚ" | |ɜɵɪɚɠɟɧɢɟ ɢɦɟɧɢ ɮɚɣɥɚ|>

xɄɨɧɫɬɚɧɬɚ ɢɦɟɧɢ ɮɚɣɥɚ ɡɚɤɥɸɱɚɟɬɫɹ ɜ ɤɚɜɵɱɤɢ (" ");

xȼɵɪɚɠɟɧɢɟ ɢɦɟɧɢ ɮɚɣɥɚ ɡɚɤɥɸɱɚɟɬɫɹ ɜ ɪɚɡɞɟɥɢɬɟɥɢ (||).

Ɍɟɤɫɬɨɜɵɟ SPICE-ɮɚɣɥɵ ɢ ɛɢɛɥɢɨɬɟɤɢ ɦɨɝɭɬ ɢɫɩɨɥɶɡɨɜɚɬɶ ɤɚɤ

|ɜɵɪɚɠɟɧɢɟ ɢɦɟɧɢ ɮɚɣɥɚ|, ɬɚɤ ɢ "ɤɨɧɫɬɚɧɬɭ ɢɦɟɧɢ ɮɚɣɥɚ". |ȼɵɪɚɠɟɧɢɟ ɢɦɟɧɢ ɮɚɣɥɚ| ɦɨɠɟɬ ɛɵɬɶ ɬɨɥɶɤɨ ɩɪɨɫɬɵɦ ɢɦɟɧɟɦ ɬɟɤɫɬɚ ɢɡ ɞɢɪɟɤɬɢɜɵ ɨɩɪɟ- ɞɟɥɟɧɢɹ ɩɨɞɫɯɟɦɵ ɜɢɞɚ TEXT: ɨɩɟɪɚɬɨɪ. Ɍɚɤɨɜ ɫɩɨɫɨɛ ɩɪɟɞɫɬɚɜɥɟɧɢɹ ɤɨɦ- ɦɟɪɱɟɫɤɢɯ ɭɫɬɪɨɣɫɬɜ ɫ ɩɪɨɝɪɚɦɦɢɪɭɟɦɨɣ ɥɨɝɢɤɨɣ, ɦɨɞɟɥɢɪɭɟɦɵɯ ɩɨɞɫɯɟɦɨɣ ɩɪɨɝɪɚɦɦɢɪɭɟɦɨɣ ɥɨɝɢɱɟɫɤɨɣ ɦɚɬɪɢɰɵ, ɫɨɞɟɪɠɚɳɟɣ ɢɦɹ JEDEC-ɮɚɣɥɚ. ɇɚ- ɩɪɢɦɟɪ:

.SUBCKT PLD24 I1 I2 O1 O2 O3 O4

+TEXT: JFILE="JD.STM"

. . .

U1 PLOR(2,4)

+$G_DPWR $G_DGND

+I1 I2 O1 O2 O3 O4

+PLAMODEL

+IO_STD_PLD

+FILE=|JFILE|

Ɂɞɟɫɶ, ɩɨɞɫɯɟɦɚ ɦɚɬɪɢɰɵ ɢɫɩɨɥɶɡɭɟɬ ɢɦɹ ɩɪɢɫɜɨɟɧɧɨɟ JEDEC-ɮɚɣɥɭ

(JFILE).

JEDEC-ɮɚɣɥɭ ɦɨɠɟɬ ɛɵɬɶ ɩɪɢɫɜɨɟɧɨ ɢɦɹ ɩɪɢ ɢɫɩɨɥɶɡɨɜɚɧɢɢ ɩɨɞɫɯɟɦɵ ɜ ɫɯɟɦɧɨɦ ɮɚɣɥɟ ɢɥɢ SPICE-ɮɚɣɥɟ ɩɭɬɟɦ ɢɫɩɨɥɶɡɨɜɚɧɢɹ ɚɬɪɢɛɭɬɚ FILE. ɂɦɹ ɦɨɠɟɬ ɢ ɧɟ ɩɪɢɫɜɚɢɜɚɬɶɫɹ, ɜ ɷɬɨɦ ɫɥɭɱɚɟ JFILE ɛɭɞɟɬ ɢɫɩɨɥɶɡɨɜɚɬɶ ɭɦɨɥɱɚ- ɬɟɥɶɧɨɟ ɢɦɹ "JD.STM". Ɇɚɬɪɢɰɵ ɜ ɫɯɟɦɧɵɯ ɮɚɣɥɚɯ, ɭ ɤɨɬɨɪɵɯ ɡɚɩɨɥɧɹɟɬɫɹ ɚɬɪɢɛɭɬ FILE, ɞɨɥɠɧɵ ɢɫɩɨɥɶɡɨɜɚɬɶ "ɤɨɧɫɬɚɧɬɭ ɢɦɟɧɢ ɮɚɣɥɚ", ɩɨɫɤɨɥɶɤɭ ɜ ɷɬɨɦ ɫɥɭɱɚɟ ɧɟɬ ɫɩɨɫɨɛɚ ɨɩɪɟɞɟɥɟɧɢɹ |ɜɵɪɚɠɟɧɢɹ ɢɦɟɧɢ ɮɚɣɥɚ|. ȿɫɥɢ ɢɫ- ɩɨɥɶɡɭɟɬɫɹ ɚɬɪɢɛɭɬ FILE, ɢɝɧɨɪɢɪɭɟɬɫɹ ɚɬɪɢɛɭɬ DATA. ɉɪɢ ɷɬɨɦ ɪɚɫɩɪɟɞɟɥɟ- ɧɢɟ ɞɚɧɧɵɯ ɜ JEDEC-ɮɚɣɥɟ ɫɜɹɡɵɜɚɟɬɫɹ ɫ ɩɚɪɚɦɟɬɪɚɦɢ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ.

<Ʉɨɧɫɬɚɧɬɚ ɞɚɧɧɵɯ> ɩɨɡɜɨɥɹɸɬ ɫɨɡɞɚɜɚɬɶ ɬɚɛɥɢɰɭ ɞɚɧɧɵɯ ɜ ɬɟɤɫɬɨɜɨɣ ɨɛɥɚɫɬɢ ɢɥɢ ɧɟɩɨɫɪɟɞɫɬɜɟɧɧɨ ɧɚ ɩɨɥɟ ɫɯɟɦɵ. Ɉɧɢ ɫɨɡɞɚɸɬɫɹ ɩɨɫɪɟɞɫɬɜɨɦ ɞɢɪɟɤɬɢɜɵ .DEFINE. Ɂɧɚɱɟɧɢɟ ɫɢɦɜɨɥɶɧɨɣ ɩɟɪɟɦɟɧɧɨɣ ɢɡ ɷɬɨɣ ɞɢɪɟɤɬɢɜɵ ɩɨɞɫɬɚɜɥɹɟɬɫɹ ɜ ɤɚɱɟɫɬɜɟ ɬɚɛɥɢɰɵ ɞɚɧɧɵɯ ɩɪɢ ɡɚɩɭɫɤɟ ɚɧɚɥɢɡɚ. ɇɚɩɪɢɦɟɪ:

.DEFINE TAB1 B$01 01 10 11 01 11 01 10 01$

ȿɫɥɢ ɩɪɨɝɪɚɦɦɢɪɭɟɦɚɹ ɦɚɬɪɢɰɚ ɢɫɩɨɥɶɡɭɟɬ ɤɨɧɫɬɚɧɬɭ ɞɚɧɧɵɯ TAB1, ɬɟɤɫɬ "B$01 01 10 11 01 11 01 10 01$" ɛɭɞɟɬ ɩɨɞɫɬɚɜɥɟɧ ɧɚ ɦɟɫɬɨ TAB1 ɩɪɢ ɡɚɩɭɫɤɟ ɚɧɚɥɢɡɚ. Ⱦɢɪɟɤɬɢɜɵ .DEFINE ɦɨɝɭɬ ɛɵɬɶ ɢɫɩɨɥɶɡɨɜɚɧɵ ɞɥɹ ɩɟɪɟɦɟ- ɳɟɧɢɹ ɞɥɢɧɧɵɯ ɨɩɪɟɞɟɥɟɧɢɣ ɜ ɚɬɪɢɛɭɬɟ DATA ɜ ɬɟɤɫɬɨɜɭɸ ɨɛɥɚɫɬɶ, ɢɥɢ ɩɪɨ- ɫɬɨ ɞɥɹ ɫɨɡɞɚɧɢɹ ɤɨɦɩɚɤɬɧɵɯ ɬɚɛɥɢɱɧɵɯ ɤɨɧɫɬɚɧɬ.

<ɩɪɢɡɧɚɤ ɫɢɫɬɟɦɵ ɫɱɢɫɥɟɧɢɹ>$ — ɩɪɢɡɧɚɤ ɫɢɫɬɟɦɵ ɫɱɢɫɥɟɧɢɹ, ɜ ɤɨ- ɬɨɪɨɣ ɡɚɩɢɫɚɧɚ ɬɚɛɥɢɰɚ ɞɚɧɧɵɯ:

Bɞɜɨɢɱɧɚɹ

Oɜɨɫɶɦɟɪɢɱɧɚɹ

Xɲɟɫɬɧɚɞɰɚɬɟɪɢɱɧɚɹ

<ɬɚɛɥɢɰɚ ɞɚɧɧɵɯ>$ — ɬɟɤɫɬɨɜɚɹ ɫɬɪɨɤɚ, ɫɨɞɟɪɠɚɳɚɹ ɞɚɧɧɵɟ ɩɪɨɝɪɚɦ- ɦɢɪɨɜɚɧɢɹ ɉɅɆ. ȿɫɥɢ ɡɧɚɱɟɧɢɟ ɞɚɧɧɵɯ ɞɥɹ ɫɨɨɬɜɟɬɫɬɜɭɸɳɟɝɨ ɜɯɨɞɧɨɝɨ ɫɬɨɥɛɰɚ ɪɚɜɧɨ 0, ɞɚɧɧɵɣ ɫɬɨɥɛɟɰ ɧɟ ɜɤɥɸɱɚɟɬɫɹ ɜ ɡɚɤɥɸɱɢɬɟɥɶɧɭɸ ɨɩɟɪɚɰɢɸ