Микросхемотехника / amelina_m_a_amelin_s_a_programma_shemotehnicheskogo_modeliro

ɩɨɷɬɨɦɭ ɜ ɩɟɪɜɭɸ ɨɱɟɪɟɞɶ ɰɟɥɟɫɨɨɛɪɚɡɧɨ ɪɚɫɫɦɨɬɪɟɬɶ ɮɨɪɦɚɬ ɡɚɞɚɧɢɹ ɰɢɮ- ɪɨɜɨɝɨ ɩɪɢɦɢɬɢɜɚ.

Ɇɨɞɟɥɶ ɰɢɮɪɨɜɨɝɨ ɤɨɦɩɨɧɟɧɬɚ (ɜ ɬɨɦ ɱɢɫɥɟ ɢ ɩɪɢɦɢɬɢɜɚ) ɫɨɫɬɨɢɬ ɢɡ ɞɜɭɯ ɱɚɫɬɟɣ: ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ (timing model) ɢ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ (I/O model). ȼɪɟɦɟɧɧɚɹ ɦɨɞɟɥɶ ɨɩɪɟɞɟɥɹɟɬ ɡɚɞɟɪɠɤɢ ɪɚɫɩɪɨɫɬɪɚɧɟɧɢɹ ɰɢɮɪɨɜɵɯ ɫɨɫɬɨɹ- ɧɢɣ ɢ ɨɝɪɚɧɢɱɟɧɢɹ ɫɧɢɡɭ ɧɚ ɞɥɢɬɟɥɶɧɨɫɬɢ ɞɟɣɫɬɜɢɹ ɰɢɮɪɨɜɵɯ ɫɢɝɧɚɥɨɜ. ɂɧ- ɬɟɪɮɟɣɫɧɚɹ ɦɨɞɟɥɶ ɨɩɪɟɞɟɥɹɟɬ ɫɨɩɪɨɬɢɜɥɟɧɢɹ, ɷɤɜɢɜɚɥɟɧɬɧɵɟ ɫɯɟɦɵ ɢ ɜɪɟɦɟɧɚ ɩɟɪɟɤɥɸɱɟɧɢɹ ɚɧɚɥɨɝɨ-ɰɢɮɪɨɜɨɝɨ ɢɧɬɟɪɮɟɣɫɚ.

ɂɧɬɟɪɮɟɣɫɧɚɹ ɦɨɞɟɥɶ (I/O model) ɢɫɩɨɥɶɡɭɟɬɫɹ ɜ ɨɫɧɨɜɧɨɦ ɩɪɢ ɫɨɟɞɢ- ɧɟɧɢɢ ɚɧɚɥɨɝɨɜɵɯ ɢ ɰɢɮɪɨɜɵɯ ɭɡɥɨɜ. Ʉɪɨɦɟ ɬɨɝɨ, ɫ ɟɟ ɩɨɦɨɳɶɸ ɪɟɲɚɟɬɫɹ

ɜɨɩɪɨɫ ɨ ɰɢɮɪɨɜɨɦ ɫɨɫɬɨɹɧɢɢ ɢ ɞɢɧɚɦɢɤɟ ɟɝɨ ɢɡɦɟɧɟɧɢɹ ɜ ɡɚɜɢɫɢɦɨɫɬɢ ɨɬ ɧɚɝɪɭɡɨɱɧɨɣ ɫɩɨɫɨɛɧɨɫɬɢ ɦɢɤɪɨɫɯɟɦɵ (ɩɪɢ ɨɛɴɟɞɢɧɟɧɢɢ ɜɵɯɨɞɨɜ ɧɟɫɤɨɥɶɤɢɯ ɭɫɬɪɨɣɫɬɜ).

Ʉɚɤ ɩɪɚɜɢɥɨ, ɢɧɬɟɪɮɟɣɫ ɜ ɩɪɟɞɟɥɚɯ ɨɞɧɨɣ ɫɟɪɢɢ ɰɢɮɪɨɜɵɯ ɦɢɤɪɨɫɯɟɦ ɫɬɚɧɞɚɪɬɢɡɢɪɨɜɚɧ. ɇɚɩɪɢɦɟɪ, ɜɫɟ ɤɨɦɩɨɧɟɧɬɵ ɫɟɪɢɢ 74LS ɢɦɟɸɬ ɨɞɢɧɚɤɨɜɵɟ ɢɧɬɟɪɮɟɣɫɧɵɟ ɫɩɟɰɢɮɢɤɚɰɢɢ, ɩɨɷɬɨɦɭ ɛɨɥɶɲɢɧɫɬɜɨ ɛɢɛɥɢɨɬɟɱɧɵɯ ɤɨɦɩɨ- ɧɟɧɬɵ ɷɬɨɣ ɫɟɪɢɢ ɛɭɞɭɬ ɢɦɟɬɶ ɨɞɧɭ ɢ ɬɭ ɠɟ ɢɧɬɟɪɮɟɣɫɧɭɸ ɦɨɞɟɥɶ. ɂɫɤɥɸɱɟ- ɧɢɹ ɢɡ ɛɨɥɶɲɢɧɫɬɜɚ ɛɭɞɭɬ ɨɬɧɨɫɢɬɶɫɹ ɤ ɤɨɦɩɨɧɟɧɬɚɦ ɫ ɨɬɤɪɵɬɵɦ ɤɨɥɥɟɤɬɨ- ɪɨɦ, ɬɪɟɯɫɬɚɛɢɥɶɧɵɦ ɫɯɟɦɚɦ, ɥɨɝɢɤɟ ɫ ɬɪɢɝɝɟɪɚɦɢ ɒɦɢɬɬɚ ɧɚ ɜɯɨɞɟ.

ȼɪɟɦɟɧɧɚɹ ɦɨɞɟɥɶ (Timing model) ɨɩɢɫɵɜɚɟɬ ɭɧɢɤɚɥɶɧɵɟ ɨɫɨɛɟɧɧɨɫɬɢ ɤɚɠɞɨɣ ɨɬɞɟɥɶɧɨ ɜɡɹɬɨɣ ɰɢɮɪɨɜɨɣ ɦɢɤɪɨɫɯɟɦɵ, ɩɨɷɬɨɦɭ ɛɨɥɶɲɢɧɫɬɜɨ ɰɢɮ-

ɪɨɜɵɯ ɤɨɦɩɨɧɟɧɬɨɜ ɢɦɟɸɬ ɪɚɡɥɢɱɧɵɟ ɜɪɟɦɟɧɧɵɟ ɦɨɞɟɥɢ ɞɚɠɟ ɜ ɩɪɟɞɟɥɚɯ ɨɞɧɨɣ ɫɟɪɢɢ ɰɢɮɪɨɜɵɯ ɦɢɤɪɨɫɯɟɦ.

Ɏɨɪɦɚɬ ɡɚɞɚɧɢɹ ɰɢɮɪɨɜɨɝɨ ɩɪɢɦɢɬɢɜɚ

U<ɢɦɹ> <ɬɢɩ ɩɪɢɦɢɬɢɜɚ> [(<ɡɧɚɱɟɧɢɟ ɩɚɪɚɦɟɬɪɚ>*)] +<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ> <ɭɡɟɥ>* +<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> <ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ> +[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>] +[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>]

ɉɪɢɦɟɪɵ:

U1 JKFF(1) $G_DPWR $G_DGND PR CLB CKB J K Q QB D0_74 IO_STD U1 NOR(3) $G_DPWR $G_DGND 10 20 30 40 D0_74 IO_STD

Ɉɩɪɟɞɟɥɟɧɢɹ

U<ɢɦɹ> — ɩɪɟɞɫɬɚɜɥɹɟɬ ɫɨɛɨɣ ɩɨɡɢɰɢɨɧɧɨɟ ɨɛɨɡɧɚɱɟɧɢɟ ɤɨɦɩɨɧɟɧɬɚ. <ɬɢɩ ɩɪɢɦɢɬɢɜɚ> — ɭɤɚɡɵɜɚɟɬ ɬɢɩ ɰɢɮɪɨɜɨɝɨ ɤɨɦɩɨɧɟɧɬɚ ɩɨ ɩɪɢɧɰɢɩɭ

ɞɟɣɫɬɜɢɹ (ɥɨɝɢɱɟɫɤɨɣ ɮɭɧɤɰɢɢ), ɤɚɤ, ɧɚɩɪɢɦɟɪ:

xNAND — ɥɨɝɢɱɟɫɤɢɣ ɷɥɟɦɟɧɬ ɂ-ɇȿ;

xNOR — ɥɨɝɢɱɟɫɤɢɣ ɷɥɟɦɟɧɬ ɂɅɂ-ɇȿ,

xJKFF — JK-ɬɪɢɝɝɟɪ, ɩɟɪɟɤɥɸɱɚɸɳɢɣɫɹ ɩɨ ɡɚɞɧɟɦɭ ɮɪɨɧɬɭ ɫɢɧɯɪɨɫɢɝɧɚɥɚ;

xPLA — ɩɪɨɝɪɚɦɦɢɪɭɟɦɚɹ ɥɨɝɢɱɟɫɤɚɹ ɦɚɬɪɢɰɚ.

[(<ɡɧɚɱɟɧɢɟ ɩɚɪɚɦɟɬɪɚ>*)] — ɡɚɜɢɫɢɬ ɨɬ ɬɢɩɚ ɰɢɮɪɨɜɨɝɨ ɩɪɢɦɢɬɢɜɚ, ɦɨɠɟɬ ɨɬɫɭɬɫɬɜɨɜɚɬɶ ɢɥɢ ɫɨɞɟɪɠɚɬɶ ɨɞɧɨ ɢɥɢ ɧɟɫɤɨɥɶɤɨ ɰɟɥɵɯ ɱɢɫɟɥ. Ɉɛɵɱ- ɧɨ ɩɪɟɞɫɬɚɜɥɹɟɬ ɫɨɛɨɣ ɱɢɫɥɨ ɜɵɜɨɞɨɜ (pin) ɰɢɮɪɨɜɨɝɨ ɤɨɦɩɨɧɟɧɬɚ ɢ (ɢɥɢ) ɱɢɫɥɨ ɩɪɢɦɢɬɢɜɨɜ ɜ ɦɚɫɫɢɜɟ.

<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ> — ɞɚɧɧɵɟ ɭɡɥɵ ɨɛɟɫɩɟɱɢɜɚɸɬ ɩɢɬɚɧɢɟ ɫɯɟɦ ɚɧɚɥɨɝɨ-ɰɢɮɪɨɜɨɝɨ ɢɧɬɟɪɮɟɣɫɚ, ɧɟɨɛɯɨɞɢɦɨɝɨ, ɤɨɝɞɚ ɚɧɚɥɨɝɨɜɵɟ ɭɡɥɵ ɫɨɟɞɢɧɹɸɬɫɹ ɫ ɰɢɮɪɨɜɵɦɢ. Ɉɛɵɱɧɨ ɢɫɩɨɥɶɡɭɸɬɫɹ ɢɦɟɧɚ ɝɥɨɛɚɥɶɧɵɯ ɭɡɥɨɜ $G_DPWR ɢ $G_DGND

<ɭɡɟɥ>* — ɢɦɟɧɚ ɭɡɥɨɜ ɤɨɦɩɨɧɟɧɬɚ, ɤɨɥɢɱɟɫɬɜɨ ɩɟɪɟɱɢɫɥɹɟɦɵɯ ɭɡɥɨɜ ɡɚɜɢɫɢɬ ɨɬ ɬɢɩɚ ɩɪɢɦɢɬɢɜɚ.

ɇɚɩɪɢɦɟɪ, ɞɥɹ ɜɟɧɬɢɥɟɣ ɩɨɪɹɞɨɤ ɫɥɟɞɭɸɳɢɣ:

IN1 IN2 ….INN ENABLE OUT;

Ɂɞɟɫɶ ɩɟɪɟɱɢɫɥɟɧɵ ɢɦɟɧɚ ɭɡɥɨɜ N ɜɯɨɞɨɜ ɜɟɧɬɢɥɹ, ɜɯɨɞɚ ɪɚɡɪɟɲɟɧɢɹ ɪɚɛɨɬɵ (ENABLE), ɜɵɯɨɞɚ ɜɟɧɬɢɥɹ (OUT).

Ⱦɥɹ D-ɬɪɢɝɝɟɪɚ:

PRESETBAR CLEARBAR CLOCK D Q QB

Ɂɞɟɫɶ ɩɟɪɟɱɢɫɥɟɧɵ ɢɦɟɧɚ ɭɡɥɨɜ ɚɫɢɧɯɪɨɧɧɨɣ ɩɪɟɞɭɫɬɚɧɨɜɤɢ

(PRESETBAR) ɢ ɫɛɪɨɫɚ (CLEARBAR), ɬɚɤɬɨɜɨɝɨ ɜɯɨɞɚ (CLOCK), ɢɧɮɨɪɦɚɰɢ-

ɨɧɧɨɝɨ ɜɯɨɞɚ D, ɩɪɹɦɨɝɨ (Q) ɢ ɢɧɜɟɪɫɧɨɝɨ (QB) ɜɵɯɨɞɨɜ.

<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> (Timing model) — ɭɤɚɡɚɧɧɨɟ ɜ ɷɬɨɣ ɫɬɪɨɤɟ ɢɦɹ ɡɚɞɚɟɬ ɫɫɵɥɤɭ ɧɚ ɫɨɨɬɜɟɬɫɬɜɭɸɳɭɸ ɦɨɞɟɥɶɧɭɸ ɞɢɪɟɤɬɢɜɭ, ɤɨɬɨɪɚɹ ɫɨɞɟɪɠɢɬ

ɡɧɚɱɟɧɢɹ ɡɚɞɟɪɠɟɤ ɪɚɫɩɪɨɫɬɪɚɧɟɧɢɹ ɫɢɝɧɚɥɚ ɢ ɨɝɪɚɧɢɱɟɧɢɹ ɧɚ ɞɥɢɬɟɥɶɧɨɫɬɶ ɫɢɝɧɚɥɨɜ. Ʉɚɠɞɚɹ ɜɪɟɦɟɧɧɚɹ ɦɨɞɟɥɶ ɢɦɟɟɬ ɦɢɧɢɦɚɥɶɧɵɟ, ɬɢɩɨɜɵɟ ɢ ɦɚɤɫɢ- ɦɚɥɶɧɵɟ ɡɧɚɱɟɧɢɹ ɫɨɨɬɜɟɬɫɬɜɭɸɳɢɯ ɩɚɪɚɦɟɬɪɨɜ. ɉɚɪɚɦɟɬɪ MNTYMXDLY ɜɵ- ɛɢɪɚɟɬ ɨɞɧɨ ɢɡ ɡɧɚɱɟɧɢɣ ɢɥɢ ɪɚɡɪɟɲɚɟɬ ɢɫɩɨɥɶɡɨɜɚɧɢɟ ɝɥɨɛɚɥɶɧɨɝɨ ɩɚɪɚɦɟɬ- ɪɚ DIGMNTYMX (ɢɡ ɭɫɬɚɧɨɜɨɤ ɞɢɚɥɨɝɨɜɨɝɨ ɨɤɧɚ Global Settings).

<ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ> (I/O model) — ɭɤɚɡɚɧɧɨɟ ɜ ɷɬɨɣ ɩɨɡɢɰɢɢ ɢɦɹ ɡɚɞɚɟɬ ɫɫɵɥɤɭ ɧɚ ɫɨɨɬɜɟɬɫɬɜɭɸɳɭɸ ɦɨɞɟɥɶɧɭɸ ɞɢɪɟɤɬɢɜɭ, ɤɨɬɨɪɚɹ ɨɩɪɟ- ɞɟɥɹɟɬ ɢɦɩɟɞɚɧɫɵ ɦɢɤɪɨɫɯɟɦɵ ɢ ɫɯɟɦɭ ɚɧɚɥɨɝɨ-ɰɢɮɪɨɜɨɝɨ ɢɧɬɟɪɮɟɣɫɚ.

[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>] — ɡɚɞɚɟɬ ɢɫɩɨɥɶɡɨɜɚɧɢɟ ɞɥɹ ɜɫɟɯ ɰɢɮɪɨɜɵɯ ɤɨɦɩɨɧɟɧɬɨɜ ɦɢɧɢɦɚɥɶɧɨɣ, ɬɢɩɨɜɨɣ, ɦɚɤɫɢɦɚɥɶɧɨɣ ɡɚɞɟɪɠɟɤ ɢɥɢ ɢɯ ɧɚɢɯɭɞɲɟɝɨ ɫɨɱɟɬɚɧɢɹ:

x0 — ɬɟɤɭɳɟɟ ɡɧɚɱɟɧɢɟ ɩɚɪɚɦɟɬɪɚ DIGMNTYMX ɞɢɚɥɨɝɨɜɨɝɨ ɨɤɧɚ Global Settings (ɩɨ ɭɦɨɥɱɚɧɢɸ DIGMNTYMX=2).

x1 — ɦɢɧɢɦɚɥɶɧɚɹ

x2 — ɬɢɩɨɜɚɹ

x3 — ɦɚɤɫɢɦɚɥɶɧɚɹ

x4 — ɧɚɢɯɭɞɲɢɣ ɫɥɭɱɚɣ. ɂɫɩɨɥɶɡɨɜɚɧɢɟ ɦɢɧɢɦɚɥɶɧɨɣ ɢ ɦɚɤɫɢɦɚɥɶɧɨɣ

ɡɚɞɟɪɠɟɤ.

[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>] — ɜɵɛɢɪɚɟɬ ɨɞɢɧ ɢɡ

4-ɯ ɬɢɩɨɜ ɢɧɬɟɪɮɟɣɫɧɵɯ ɦɨɞɟɥɟɣ (ɬɚɛɥ. 13.4), ɢɫɩɨɥɶɡɭɟɦɵɯ ɜ ɫɦɟɲɚɧɧɨɦ ɦɨɞɟɥɢɪɨɜɚɧɢɢ.

Ɏɨɪɦɚɬ ɞɢɪɟɤɬɢɜɵ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ (Timing model):

.MODEL <ɢɦɹ ɦɨɞɟɥɢ> <ɬɢɩ ɦɨɞɟɥɢ> (<ɩɚɪɚɦɟɬɪ ɦɨɞɟɥɢ>*)

Ʉɚɠɞɵɣ ɬɢɩ ɩɪɢɦɢɬɢɜɨɜ ɢɦɟɟɬ ɭɧɢɤɚɥɶɧɵɣ <ɬɢɩ ɦɨɞɟɥɢ> ɢ ɧɚɛɨɪ ɩɚɪɚ- ɦɟɬɪɨɜ ɦɨɞɟɥɢ.

Ɏɨɪɦɚɬ ɞɢɪɟɤɬɢɜɵ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ (I/O model):

.MODEL <ɢɦɹ ɦɨɞɟɥɢ> UIO (<ɩɚɪɚɦɟɬɪ ɦɨɞɟɥɢ>*) — ɨɛɳɚɹ ɫɬɪɭɤɬɭɪɚ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ, ɢɫɩɨɥɶɡɭɟɦɚɹ ɜɫɟɦɢ ɩɪɢɦɢɬɢɜɚɦɢ.

ɜɚɬɶ (ɜɵɛɢɪɚɬɶ ɢɡ ɫɩɢɫɤɚ) ɜɪɟɦɟɧɧɭɸ ɦɨɞɟɥɶ (TIMING MODEL) ɢ ɢɧɬɟɪɮɟɣɫ- ɧɭɸ ɦɨɞɟɥɶ (I/O MODEL) ɉɪɢ ɢɫɩɨɥɶɡɨɜɚɧɢɢ ɛɢɛɥɢɨɬɟɱɧɵɯ ɤɨɦɩɨɧɟɧɬɨɜ ɷɬɨ- ɝɨ ɧɟ ɬɪɟɛɭɟɬɫɹ, ɩɨɫɤɨɥɶɤɭ ɨɩɢɫɚɧɢɟ ɛɢɛɥɢɨɬɟɱɧɨɝɨ ɤɨɦɩɨɧɟɧɬɚ, ɡɚɞɚɧɧɨɟ ɜ ɛɢɛɥɢɨɬɟɤɟ DIGXXXX.LIB, ɭɠɟ ɫɨɞɟɪɠɢɬ ɫɫɵɥɤɢ ɧɚ ɫɨɨɬɜɟɬɫɬɜɭɸɳɢɟ ɜɪɟɦɟɧ- ɧɵɟ ɢ ɢɧɬɟɪɮɟɣɫɧɵɟ ɦɨɞɟɥɢ.

SPICE-ɨɩɢɫɚɧɢɟ ɰɢɮɪɨɜɨɝɨ ɤɨɦɩɨɧɟɧɬɚ ɫɬɪɨɢɬɫɹ ɩɨ ɦɨɞɭɥɶɧɨɦɭ ɩɪɢɧɰɢ- ɩɭ. ɋɭɳɟɫɬɜɭɟɬ ɨɩɪɟɞɟɥɟɧɧɵɣ ɧɚɛɨɪ ɩɨɞɫɯɟɦ ɞɥɹ ɮɨɪɦɢɪɨɜɚɧɢɹ ɜɪɟɦɟɧɧɵɯ ɢ ɢɧɬɟɪɮɟɣɫɧɵɯ ɦɨɞɟɥɟɣ. Ɋɚɡɧɚɹ ɤɨɦɛɢɧɚɰɢɹ ɷɬɢɯ ɩɨɞɫɯɟɦ ɢ ɪɚɡɧɵɣ ɧɚɛɨɪ ɢɯ ɩɚɪɚɦɟɬɪɨɜ ɮɨɪɦɢɪɭɟɬ ɩɨɥɧɭɸ ɦɨɞɟɥɶ ɤɨɧɤɪɟɬɧɨɝɨ ɤɨɦɩɨɧɟɧɬɚ. ɋɬɪɭɤɬɭɪɚ ɩɨɥɧɨɣ ɦɨɞɟɥɢ ɧɚ ɩɪɢɦɟɪɟ ɰɢɮɪɨɜɨɝɨ ɤɨɦɩɨɧɟɧɬɚ 7410 ɩɪɟɞɫɬɚɜɥɟɧɚ ɧɚ ɪɢɫ. 13.12.

ɉɨɞɫɯɟɦɚ ɤɨɦɩɨɧɟɧɬɚ 7410 (3ɂ-ɇȿ) ɢ ɟɟ ɜɪɟɦɟɧɧɚɹ ɦɨɞɟɥɶ (TIMING MODEL) ɧɚɯɨɞɹɬɫɹ ɜ ɛɢɛɥɢɨɬɟɱɧɨɦ ɮɚɣɥɟ DIG000.LIB. Ⱦɥɹ ɬɨɝɨ ɱɬɨɛɵ MicroCap ɦɨɝ ɜɨɫɩɨɥɶɡɨɜɚɬɶɫɹ ɷɬɨɣ ɛɢɛɥɢɨɬɟɤɨɣ, ɨɧɚ ɨɛɹɡɚɬɟɥɶɧɨ ɞɨɥɠɧɚ ɛɵɬɶ ɜɯɨɞɢɬɶ ɜ ɫɩɢɫɨɤ ɢɫɩɨɥɶɡɭɟɦɵɯ ɛɢɛɥɢɨɬɟɤ, ɤɨɬɨɪɵɣ ɡɚɞɚɟɬɫɹ ɮɚɣɥɨɦ NOM.LIB. Ʌɸɛɭɸ ɧɨɜɭɸ ɛɢɛɥɢɨɬɟɤɭ ɩɟɪɟɞ ɢɫɩɨɥɶɡɨɜɚɧɢɟɦ ɧɟɨɛɯɨɞɢɦɨ ɩɪɨ-

ɩɢɫɚɬɶ ɜ ɷɬɨɦ ɮɚɣɥɟ ɩɪɢ ɩɨɦɨɳɢ ɬɟɤɫɬɨɜɨɝɨ ɪɟɞɚɤɬɨɪɚ ɥɢɛɨ ɫɨɛɫɬɜɟɧɧɨɝɨ ɪɟɞɚɤɬɨɪɚ Micro-Cap.

ɂɧɬɟɪɮɟɣɫɧɚɹ ɦɨɞɟɥɶ (I/O MODEL), ɦɨɞɟɥɢ ATOD ɢ DTOA ɢɧɬɟɪɮɟɣɫɨɜ, ɦɨɞɟɥɢ N-ɤɨɦɩɨɧɟɧɬɚ ɢ O-ɤɨɦɩɨɧɟɧɬɚ ɢ ɩɨɞɫɯɟɦɵ ɩɢɬɚɧɢɹ ɢɧɬɟɪɮɟɣɫɚ ɧɚɯɨ- ɞɹɬɫɹ ɜ ɛɢɛɥɢɨɬɟɱɧɨɦ ɮɚɣɥɟ DIGIO.LIB, ɤɨɬɨɪɵɣ ɬɚɤɠɟ ɫɨɞɟɪɠɢɬɫɹ ɜ ɫɩɢɫɤɟ

NOM.LIB.

13.2.3. ɐɢɮɪɨɜɵɟ SPICE-ɩɪɢɦɢɬɢɜɵ, ɢɫɩɨɥɶɡɭɸɳɢɟɫɹ ɜ Micro-Cap

ɐɢɮɪɨɜɵɟ SPICE-ɩɪɢɦɢɬɢɜɵ, ɢɫɩɨɥɶɡɭɸɳɢɟɫɹ ɜ Micro-Cap, ɩɪɟɞɫɬɚɜɥɟ- ɧɵ ɜ ɬɚɛɥɢɰɟ 13.5.

Ɍ ɚ ɛ ɥ ɢ ɰ ɚ 1 3 . 5 . ɐɢɮɪɨɜɵɟ SPICE-ɩɪɢɦɢɬɢɜɵ

ɋɥɟɞɭɟɬ ɨɬɦɟɬɢɬɶ, ɱɬɨ ɰɢɮɪɨɜɵɟ ɩɪɢɦɢɬɢɜɵ, ɢɦɟɸɳɢɟɫɹ ɜ ɫɨɫɬɚɜɟ

Micro-Cap (ɜɵɛɢɪɚɟɦɵɟ ɢɡ ɪɚɡɞɟɥɚ COMPONENT>Digital Primitives), ɢɦɟɸɬ ɧɚɡɜɚɧɢɹ, ɨɬɥɢɱɚɸɳɢɟɫɹ ɨɬ ɩɪɢɜɟɞɟɧɧɵɯ ɜ ɬɚɛɥ. 13.5. Ɉɞɧɚɤɨ ɜ ɤɚɱɟɫɬɜɟ ɦɨ- ɞɟɥɢ ɨɧɢ ɬɚɤɠɟ ɢɫɩɨɥɶɡɭɸɬ ɰɢɮɪɨɜɨɣ SPICE-ɩɪɢɦɢɬɢɜ. ɇɚɩɪɢɦɟɪ, ɫɤɚɡɚɧɧɨɟ ɨɬɧɨɫɢɬɫɹ ɤ ɰɢɮɪɨɜɨɦɭ ɩɪɢɦɢɬɢɜɭ Xnor_T (ɪɚɡɞɟɥ COMPONENT>Digital Primitives>Tri-State Gates>Xnor_Tri Gates). ȿɫɥɢ, ɡɚɣɞɹ ɜ ɪɟɞɚɤɬɨɪ ɤɨɦɩɨɧɟɧ- ɬɨɜ (WINDOWS>Component Editor) ɩɨɫɦɨɬɪɟɬɶ ɜ ɝɪɚɮɟ Definition ɟɝɨ ɨɩɪɟɞɟ-

ɥɟɧɢɟ, ɬɨ ɦɨɠɧɨ ɭɜɢɞɟɬɶ ɢɦɹ ɫɨɨɬɜɟɬɫɬɜɭɸɳɟɝɨ SPICE-ɩɪɢɦɢɬɢɜɚ NXOR3.

13.2.4.Ʌɨɝɢɱɟɫɤɢɟ ɜɟɧɬɢɥɢ (Gates)

ȼɩɪɨɝɪɚɦɦɟ Micro-Cap ɫɭɳɟɫɬɜɭɸɬ ɦɨɞɟɥɢ ɞɜɭɯ ɬɢɩɨɜ ɜɟɧɬɢɥɟɣ: ɫɬɚɧ- ɞɚɪɬɧɵɟ ɢ ɫ ɬɪɟɦɹ ɫɨɫɬɨɹɧɢɹɦɢ ɜɵɯɨɞɨɜ:

ɍɫɬɚɧɞɚɪɬɧɵɯ ɜɟɧɬɢɥɟɣ ɪɚɛɨɬɚ ɜɵɯɨɞɨɜ ɪɚɡɪɟɲɟɧɚ ɜɫɟ ɜɪɟɦɹ. ɂɯ ɜɵ- ɯɨɞɧɨɟ ɫɨɩɪɨɬɢɜɥɟɧɢɟ ɨɩɪɟɞɟɥɹɟɬɫɹ ɫɥɟɞɭɸɳɢɦ ɨɛɪɚɡɨɦ:

ɗɥɟɦɟɧɬɵ ɫ ɨɬɤɪɵɬɵɦ ɤɨɥɥɟɤɬɨɪɨɦ ɦɨɞɟɥɢɪɭɸɬɫɹ ɤɚɤ ɪɚɡɧɨɜɢɞɧɨɫɬɶ ɫɬɚɧɞɚɪɬɧɵɯ ɜɟɧɬɢɥɟɣ ɫ ɨɱɟɧɶ ɛɨɥɶɲɢɦ ɡɧɚɱɟɧɢɟɦ DRVH ɜ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ (I/O Model).

ɍ ɬɪɟɯɫɬɚɛɢɥɶɧɵɯ ɜɟɧɬɢɥɟɣ ɢɦɟɟɬɫɹ ɜɯɨɞ ɪɚɡɪɟɲɟɧɢɹ ɪɚɛɨɬɵ ɜɵɯɨɞɧɵɯ ɛɭɮɟɪɨɜ Enable. Ɏɚɤɬɢɱɟɫɤɢ ɩɨɹɜɥɟɧɢɟ ɥɨɝɢɱɟɫɤɨɝɨ ɫɢɝɧɚɥɚ ɧɚ ɜɵɯɨɞɟ ɪɚɡ- ɪɟɲɚɸɬɫɹ ɩɪɢ ɚɤɬɢɜɧɨɦ ɭɪɨɜɧɟ Enable. ȼɵɯɨɞɧɨɟ ɫɨɩɪɨɬɢɜɥɟɧɢɟ ɬɚɤɨɝɨ ɜɟɧ- ɬɢɥɹ ɨɩɪɟɞɟɥɹɟɬɫɹ ɫɥɟɞɭɸɳɢɦ ɨɛɪɚɡɨɦ:

ɋɬɚɧɞɚɪɬɧɵɟ ɢ ɬɪɟɯɫɬɚɛɢɥɶɧɵɟ ɜɟɧɬɢɥɢ ɦɨɝɭɬ ɡɚɞɚɜɚɬɶɫɹ ɥɢɛɨ ɜ ɜɢɞɟ ɨɞɢɧɨɱɧɵɯ ɜɟɧɬɢɥɟɣ, ɥɢɛɨ ɜ ɜɢɞɟ ɦɚɫɫɢɜɚ.

Ʉ ɪɚɫɫɦɚɬɪɢɜɚɟɦɵɦ ɜɟɧɬɢɥɹɦ ɩɪɢɦɟɧɹɸɬɫɹ ɩɪɚɜɢɥɚ ɨɩɟɪɚɰɢɣ ɚɥɝɟɛɪɵ ɥɨɝɢɤɢ. ȿɫɥɢ ɨɞɢɧ ɢɡ ɜɯɨɞɨɜ ɜɟɧɬɢɥɹ ɢɦɟɟɬ ɧɟɨɩɪɟɞɟɥɟɧɧɨɟ ɫɨɫɬɨɹɧɢɟ, ɭɪɨ- ɜɟɧɶ ɧɚ ɜɵɯɨɞɟ ɜɵɱɢɫɥɹɟɬɫɹ ɞɥɹ ɞɜɭɯ ɜɚɪɢɚɧɬɨɜ ɫɨɫɬɨɹɧɢɹ ɞɚɧɧɨɝɨ ɜɯɨɞɚ: «0» ɢ «1», ɫɨɝɥɚɫɧɨ ɨɛɵɱɧɵɦ Ȼɭɥɟɜɫɤɢɦ ɩɪɚɜɢɥɚɦ. ȿɫɥɢ ɫɨɫɬɨɹɧɢɹ ɜɵɯɨɞɚ ɞɥɹ ɷɬɢɯ ɞɜɭɯ ɜɚɪɢɚɧɬɨɜ ɪɚɡɥɢɱɚɸɬɫɹ, ɬɨɝɞɚ ɫɱɢɬɚɟɬɫɹ, ɱɬɨ ɧɚ ɜɵɯɨɞɟ ɫɨ- ɫɬɨɹɧɢɟ «X». ɋɤɚɡɚɧɧɨɟ ɦɨɠɧɨ ɜɵɪɚɡɢɬɶ ɩɪɢɜɟɞɟɧɧɵɦɢ ɧɢɠɟ ɪɚɫɲɢɪɟɧɧɵɦɢ ɩɪɚɜɢɥɚɦɢ:

Ɍɢɩɵ ɫɬɚɧɞɚɪɬɧɵɯ ɢ ɬɪɟɯɫɬɚɛɢɥɶɧɵɯ ɜɟɧɬɢɥɟɣ ɩɪɢɜɟɞɟɧɵ ɜ ɬɚɛɥ. 13.6. ȼ ɧɟɣ ɩɪɢɧɹɬɵ ɫɥɟɞɭɸɳɢɟ ɨɛɨɡɧɚɱɟɧɢɹ:

xen — ɜɯɨɞ ɪɚɡɪɟɲɟɧɢɹ ɪɚɛɨɬɵ ɜɵɯɨɞɧɵɯ ɛɭɮɟɪɨɜ ɜ ɬɪɟɯɫɬɚɛɢɥɶɧɵɯ ɫɯɟɦɚɯ

xin — ɨɞɢɧ ɜɯɨɞɧɨɣ ɜɵɜɨɞ

xin* — ɨɞɢɧ ɢɥɢ ɛɨɥɟɟ ɜɯɨɞɧɵɯ ɜɵɜɨɞɨɜ

xout — ɨɞɢɧ ɜɵɯɨɞɧɨɣ ɜɵɜɨɞ

xout* — ɨɞɢɧ ɢɥɢ ɛɨɥɟɟ ɜɵɯɨɞɧɵɯ ɜɵɜɨɞɨɜ

Ɍ ɚ ɛ ɥ ɢ ɰ ɚ 1 3 . 6 . Ɍɢɩɵ ɥɨɝɢɱɟɫɤɢɯ ɜɟɧɬɢɥɟɣ

Ɏɨɪɦɚɬ SPICE

U<ɢɦɹ> <ɬɢɩ ɜɟɧɬɢɥɹ>[(<ɩɚɪɚɦɟɬɪɵ>)*] +<ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ> <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ>

+<ɭɡɟɥ ɜɯɨɞɚ>* [<ɭɡɟɥ ɜɯɨɞɚ ɪɚɡɪɟɲɟɧɢɹ enable>]< ɭɡɟɥ ɜɵɯɨɞɚ>* +<ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> < ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ> +[MNTYMXDLY=<ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>]

+[IO_LEVEL=<ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>]

ɉɪɢɦɟɪɵ:

5-ɜɯɨɞɨɜɨɣ ɷɥɟɦɟɧɬ ɂɅɂ-ɇȿ:

U1 NOR(5) $G_DPWR $G_DGND IN1 IN2 IN3 IN4 IN5 OUT D0_GATE IO_STD MNTYMXDLY=0 IO_LEVEL=2

3 ɞɜɭɯɜɯɨɞɨɜɵɯ ɷɥɟɦɟɧɬɚ ɂ-ɇȿ:

U17 NANDA(2,3) $G_DPWR $G_DGND 1A 1B 2A 2B 3A 3B O1 O2 O3 DLY1 IO_ACT

2 ɷɥɟɦɟɧɬɚ 3ɂ, ɨɛɴɟɞɢɧɟɧɧɵɯ ɩɨ ɂɅɂ:

UCMPD AO(3,2) $G_DPWR $G_DGND i1a i1b i1c i2a i2b i2c out dlymod io_hc_oc MNTYMXDLY=3

ɗɥɟɦɟɧɬ 3ɂɅɂ-ɇȿ c ɬɪɟɯɫɬɚɛɢɥɶɧɵɦ ɜɵɯɨɞɨɦ:

U20 NOR3(3) $G_DPWR $G_DGND IN1 IN2 IN3 ENABLE OUT D0_GATE IO_STD MNTYMXDLY=0 IO_LEVEL=2

Ɇɚɫɫɢɜ ɢɡ ɬɪɟɯ ɷɥɟɦɟɧɬɨɜ 2ɂ-ɇȿ:

UBX AND3A(2,3) $G_DPWR $G_DGND 1A 1B 2A 2B 3A 3B EN O1 O2 O3 DLY1 IO_ACT

Ɏɨɪɦɚɬ ɫɯɟɦ Micro-Cap

xɬɪɢɛɭɬ PART: <ɢɦɹ> ɉɪɢɦɟɪ: U1

xɬɪɢɛɭɬ TIMING MODEL: <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ>

ɉɪɢɦɟɪ: 74LS

xɬɪɢɛɭɬ I/O MODEL: < ɢɦɹ ɢɧɬɟɪɮɟɣɫɧɨɣ ɦɨɞɟɥɢ>

ɉɪɢɦɟɪ: IO_STD

xɬɪɢɛɭɬ MNTYMXDLY: <ɫɟɥɟɤɬɨɪ ɡɚɞɟɪɠɤɢ>

ɉɪɢɦɟɪ: 2

xɬɪɢɛɭɬ IO_LEVEL: <ɫɟɥɟɤɬɨɪ ɩɨɞɫɯɟɦɵ ɢɧɬɟɪɮɟɣɫɚ>

ɉɪɢɦɟɪ: 1

xɬɪɢɛɭɬ POWER NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɩɢɬɚɧɢɹ>

ɉɪɢɦɟɪ: $G_DPWR

xɬɪɢɛɭɬ GROUND NODE: <ɰɢɮɪɨɜɨɣ ɭɡɟɥ ɡɟɦɥɢ>

ɉɪɢɦɟɪ: $G_DGND

Ɍ ɚ ɛ ɥ ɢ ɰ ɚ 1 3 . 7 . ɉɚɪɚɦɟɬɪɵ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ ɜɟɧɬɢɥɟɣ, ɫ

Ɏɨɪɦɚɬ ɞɢɪɟɤɬɢɜɵ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ (Timing Model)

Ⱦɥɹ ɫɬɚɧɞɚɪɬɧɨɝɨ ɜɟɧɬɢɥɹ:

.MODEL <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> UGATE ([ɩɚɪɚɦɟɬɪɵ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ])

Ⱦɥɹ ɬɪɟɯɫɬɚɛɢɥɶɧɨɝɨ ɜɟɧɬɢɥɹ:

.MODEL <ɢɦɹ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ> UTGATE ([ɩɚɪɚɦɟɬɪɵ ɜɪɟɦɟɧɧɨɣ ɦɨɞɟɥɢ])

ɉɪɢɦɟɪɵ:

.MODEL TOR UGATE ( TPLHMN=3ns TPLHTY=5ns TPLHMX=7ns + TPHLMN=4ns TPHLTY=6ns TPHLMX=7ns )

.MODEL TRIG UTGATE ( TPLHMN=2ns TPLHTY=3ns TPLHMX=5ns + TPZLMN=4ns TPZLTY=6ns TPZLMX=8ns )

13.2.5.Ɍɪɢɝɝɟɪɵ

ȼɫɨɫɬɚɜɟ ɛɢɛɥɢɨɬɟɤɢ ɰɢɮɪɨɜɵɯ ɩɪɢɦɢɬɢɜɨɜ ɢɦɟɸɬɫɹ ɬɪɢɝɝɟɪɵ ɫ ɞɢɧɚ- ɦɢɱɟɫɤɢɦ ɜɯɨɞɨɦ, ɦɟɧɹɸɳɢɟ ɫɨɫɬɨɹɧɢɟ ɩɨ ɮɪɨɧɬɭ (ɫɪɟɡɭ) ɫɢɧɯɪɨɢɦɩɭɥɶɫɚ (Flip-flops). Ʉ ɬɚɤɢɦ ɬɪɢɝɝɟɪɚɦ ɨɬɧɨɫɹɬɫɹ ɷɥɟɦɟɧɬɵ: DFF — D-ɬɪɢɝɝɟɪ, ɩɟɪɟ- ɤɥɸɱɚɸɳɢɣɫɹ ɩɨ ɮɪɨɧɬɭ ɫɢɧɯɪɨɢɦɩɭɥɶɫɚ; JKFF — JK-ɬɪɢɝɝɟɪ, ɩɟɪɟɤɥɸɱɚɸ- ɳɢɣɫɹ ɩɨ ɫɪɟɡɭ ɫɢɧɯɪɨɢɦɭɥɶɫɚ. Ɉɛɚ ɬɢɩɚ ɬɪɢɝɝɟɪɨɜ ɫ ɞɢɧɚɦɢɱɟɫɤɢɦ ɫɢɧɯɪɨɜ- ɯɨɞɨɦ ɢɦɟɸɬ ɫɬɚɬɢɱɟɫɤɢɟ ɚɫɢɧɯɪɨɧɧɵɟ ɜɯɨɞɵ ɭɫɬɚɧɨɜɤɢ (setbar) ɢ ɫɛɪɨɫɚ (clearbar) ɫ ɚɤɬɢɜɧɵɦ ɧɢɡɤɢɦ ɭɪɨɜɧɟɦ. ȼ ɬɚɛɥ. 13.8 ɢ 13.9 ɩɨɤɚɡɚɧ ɚɥɝɨɪɢɬɦ ɮɭɧɤɰɢɨɧɢɪɨɜɚɧɢɹ ɬɪɢɝɝɟɪɨɜ JKFF ɢ DFF. ȼ ɧɢɯ ɢɦɹ ɜɵɯɨɞɚ ɬɪɢɝɝɟɪɚ ɫɨ ɲɬɪɢɯɨɦ ɨɛɨɡɧɚɱɚɟɬ ɟɝɨ ɩɪɟɞɵɞɭɳɟɟ ɫɨɫɬɨɹɧɢɟ.

Ɍɚ ɛ ɥ ɢ ɰ ɚ 1 3 . 8 . Ɍɚɛɥɢɰɚ ɢɫɬɢɧɧɨɫɬɢ ɬɪɢɝɝɟɪɚ JKFF

Ɍ ɚ ɛ ɥ ɢ ɰ ɚ 1 3 . 9 . Ɍɚɛɥɢɰɚ ɢɫɬɢɧɧɨɫɬɢ ɬɪɢɝɝɟɪɚ DFF