- •Contents
- •Preface
- •About This Guide
- •Finding Information in This Guide
- •Other Sources of Information
- •Related Manuals
- •Customer Education Services
- •Syntax Conventions
- •Understanding How the SDF Annotator Works
- •$sdf_annotate System Task Syntax
- •Examples: Calling the SDF Annotator
- •Using the Configuration File
- •Timing Keywords
- •INTERCONNECT_MIPD Keyword
- •MTM Keyword
- •SCALE_FACTORS Keyword
- •SCALE_TYPE Keyword
- •TURNOFF_DELAY Keyword
- •MODULE Keyword
- •MAP_INNER Keyword
- •Using the SDF File
- •Understanding the SDF File
- •SDF File Conventions
- •Using Characters
- •OVI Standard SDF Keywords
- •SDF Keywords for Verilog-XL
- •SDF Keywords for Verifault-XL
- •SDF Version 1.* Constructs
- •SDF Version 2.* Constructs
- •SDF Version 3.* Constructs
- •SDF File Keyword Constructs
- •DELAYFILE Keyword
- •CELL Keyword and Constructs
- •DELAY Keyword and Constructs
- •ABSOLUTE Keyword
- •INCREMENT Keyword
- •PATHPULSE Keyword
- •PATHPULSEPERCENT Keyword
- •TIMINGCHECK Keyword and Constructs
- •TIMINGENV Keyword and Constructs
- •SDF File Examples
- •Example 1
- •Example 2
- •Example 3
- •+sdf_cputime
- •+sdf_error_info
- •+sdf_ign_timing_edge
- •+sdf_nocheck_ celltype
- •+sdf_no_errors
- •+sdf_nomsrc_int
- •+sdf_no_warnings
- •+sdf_split_two_timing_check +sdf_splitvlog_splitsuh +sdf_splitvlog_splitrecrem
- •+sdf_verbose
- •Additional Plus Options that Control the SDF Annotator
- •Improving SDF Annotator Performance and Memory Use
- •Removing Module Mapping
- •Disabling Multisource Interconnect Timing Resolution
- •Using Pre-scaled Delays
- •Synchronizing Time Scales
- •Synchronizing Precision
- •Processing Without Verbose Annotation
- •Using (INSTANCE *)
- •Grouping Redundant Constructs
- •Removing Zero-Delay MIPDs, MITDs, and SITDs
- •Working with Verilog-XL SDF Annotator Restrictions
- •Reverting to Original Timing Limitation
- •PATHPULSE Limitation for Interconnect Delays
- •COND Keyword Matching Condition Restriction
- •TIMESCALE Keyword Restriction in SDF File Header
- •Multiple Delay Data Limitations
- •Error Messages
- •Warning Messages
- •Overview
- •Valid Interconnect Combinations
- •Invalid Interconnect Combinations
- •Index
SDF Annotator Guide
3
Using the SDF File
This chapter describes the following:
■Understanding the SDF File on page 30
■SDF File Conventions on page 31
■OVI SDF Specification Tool Compatibility on page 34
■OVI SDF Specification Version Differences on page 36
■SDF File Keyword Constructs on page 38
■SDF File Examples on page 82
Understanding the SDF File
The SDF file is an ASCII text file that stores the timing data generated by the Verilog family tool. The SDF file can contain either a pre-layout or post-layout timing data.
The timing data in the SDF file is independent of the Verilog family tool and can include the following:
Delays |
Timing Checks |
Data |
Parameters |
|
|
|
|
Module path |
Setup |
Design |
Scaling |
Device |
Hold |
Instance |
Environmental |
Interconnect |
Recovery |
Type |
Technological |
Port |
Removal |
Library |
|
Incremental |
Skew |
|
|
Absolute |
Width |
|
|
Conditional |
Conditional |
|
|
Unconditional |
Unconditional |
|
|
|
|
|
|
January 2001 |
30 |
Product Version 3.2 |