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Национальный исследовательский университет «МИЭТ»

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SDF Annotator Guide

Index

Symbols

$sdf_annotate system task 12 example 15

+annotate_any_time 89 +maxdelays 89 +mindelays 89

+multisource_int_delays 51, 53, 55, 89 +neg_tchk 64, 90 +no_pulse_int_backanno 90 +notimingchecks 90

+pulse_e/n 90 +pulse_int_e/n 91 +pulse_int_r/m 91 +pulse_r/m 90 +sdf_cputime 86 +sdf_error_info 86 +sdf_file 12, 87 +sdf_ign_timing_edge 87 +sdf_no_errors 87 +sdf_no_warnings 88

+sdf_nocheck_celltype 87, 93 +sdf_nomsrc_int 88, 92 +sdf_verbose 13, 88, 94 +transport_int_delays 50, 53, 55, 91 +typdelays 91

ABSOLUTE keyword			44
adding values to existing delays				44
annotating
delay values	13
example call	14
using Verilog-XL			85
annotation process		10
ARRIVAL keyword		77
asynchronous control signal
active edge of clock transition				66
limit 65
average
interconnect delay			20
turn-off delay	23

binary operators 33 bit-wise characters 32

case operators		32
CCOND keyword 64, 68
CELL keyword		41
example	42
CELLTYPE keyword
disabling to improve performance					93
example	42
characters 31, 32, 34
circuit
analyzing timing behavior 77, 78
input signal applied during intended
operation			77
output signal applied during intended
operation			78
waveform applied during intended
operation			80
clock transition
asynchronous control signal limit					65
between active edge and asynchronous
control signal 66
constraining port signals against					74
defining	80
duration between edges				69
minimum interval after				63
minimum interval before				62
nochange	71
commenting in an SDF file				33
COND keyword		48, 61
example	83
restriction	95
CONDELSE keyword			48
configuration file		16
argument	13
example	16

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DATE keyword			40
default mappings				18
DELAY keyword				43
example		44
DELAYFILE keyword						39
delays
adding values to existing delays								44
calculated over path to the delay
	constraints					79
conditional			48
device	56
edge transitions					44, 45
for a complete net						54
gate	56
improving performance
grouping by type 94
removing interconnect and port
		delays			94
using pre-scaled						93
interconnect				20, 49
maximum between two signals								68
maximum difference between two
	paths			76
maximum sum of two or more								75
min:typ:max triplets						45
module		56
MTM keyword values							21
on a path		45
replacing values in existing delays 44
restrictions on multiple							96
syntax	43
turn-off		23
wire path		52
DEPARTURE keyword						78
DESIGN keyword				40
device delay		54, 56
DEVICE keyword				56
example		57
DIFF keyword			76
divider
hierarchical			33
DIVIDER keyword					40

edge identifiers restrictions 96

error limit 46 escape character 33

gate delay 56 GLOBALPATHPULSE keyword 60

HDL module name equivalent 42
header keywords	39
hierarchical design
annotating 13
hierarchy divider	33
HOLD keyword	63

INCLUDE keyword		37
INCREMENT keyword 44
example	44
indicating 13
INSTANCE keyword		42
INSTANCE keyword, example 42
interconnect
disabling multi-source interconnect
timing resolution			93
interconnect delays		20
example	20
on input ports 49
INTERCONNECT keyword			52
example	52

INTERCONNECT_MIPD keyword 20 IOPATH keyword 45, 48

COND keyword restriction 95 example 44, 46, 83

keywords ABSOLUTE 44 ARRIVAL 77 CCOND 64, 68 CELL 41 CELLTYPE 42 COND 48, 61

January 2001

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CONDELSE 48		VOLTAGE 40
DATE	40	WAVEFORM 80
DELAY	43	WIDTH 69

DELAYFILE		39
DEPARTURE		78				L
DESIGN	40, 56					L
DIFF 76
DIVIDER	40					log file	13
GLOBALPATHPULSE					60	logic constraints		77
HOLD 63						logical operators		33
INCLUDE	37
INCREMENT		44				M
INSTANCE 42						M
INTERCONNECT			52
INTERCONNECT_MIPD 20						MAP_INNER keyword				24
IOPATH	48					example 25
MAP_INNER		24				mapping timing data
MODULE	24					modules 24
NETDELAY		54				Verifault-XL defaults				18
NOCHANGE		71				Verilog-XL defaults				18
OVI SDF standard				34		Veritime defaults			19
PATHCONSTRAINT				72		maximum
PATHPULSE		58				delay between two signals 68
PERIOD	70					delay on a path			72
PERIODCONSTRAINT					74	delay values		13
PORT 49						difference between delays of two
PROCESS 40							paths	76
PROGRAM		40				interconnect delay				20
RECOVERY		65				MTM keyword		21
RECREM	67					signal cycle 74
REMOVAL 66						sum of two or more path delays					75
RETAIN	49					time scale 14
SCALE_FACTORS 21, 22						time scaling		22
SCALE_TYPE 21, 22						turn-off delay		23
SCOND	64, 68					memory
SDFVERSION 40						improving use		91
SETUP 62						min:typ:max triples			44
SETUPHOLD		64				min:typ:max triplets			45
SKEW 68						minimum
SKEWCONSTRAINT					74	delay values		13
SLACK 79						interconnect delay				20
SUM 75						interval after a clock transition					63
TEMPERATURE			41			interval before a clock transition					62
TIMESCALE		41				MTM keyword		21
TIMINGCHECK			60			time scale 14
TIMINGENV		72				time scaling		22
TURNOFF_DELAY				23		turn-off delay		23
VENDOR	40					MIPD	53, 55
Verifault-XL SDF			36			MITD	50, 53
Verilog-XL SDF			35			module	14
VERSION	40					module delay 56

January 2001

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MODULE keyword 24 example 25

module mapping

removing to improve performance 92 module path

conditional delays 48 multisource nets 50

negative timing check	90
net delay 54
NETDELAY keyword	54
example 54
NOCHANGE keyword	71

operators binary 33 case 32 logical 33

precedence 33 relational 33 unary 33

overrides

mapping specifications 25 MTM keyword 21

SCALE_FACTORS keyword 21, 22, 23, 24, 25, 45, 48, 50, 52, 54, 57, 59, 61

SCALE_TYPE keyword 21, 22, 23, 24, 25, 45, 48, 50, 52, 54, 57, 59, 61

OVI SDF standard keywords 34

PATHCONSTRAINT keyword						72
PATHPULSE keyword				58, 95
example	59
limitation	95
PATHPULSEPERCENT keyword							60
Performance improvement
removing module mapping						92
performance improvement
disabling celltype verification							93
disabling multi-source interconnect
timing resolution					92
grouping delays of a certain type 94
not using +sdf_verbose					94
pre-scaled delays			93
removing interconnect or port
delays		94
synchronizing time scales						93
using INSTANCE *				94
performance improvements					91
synchronizing precision					93
PERIOD keyword		70
PERIODCONSTRAINT keyword							74
PORT keyword 49
example	44, 50
ports
invalid source and destination
combinations				115
valid source and destination
combinations				102
precision
improving performance by
synchronizing				93
PROCESS keyword			40
PROGRAM keyword			40
pulse
error limit	59
rejection and error limits					90
rejection limit		59

path
conditional module path delays			48
delays 45
limits between ports 58
maximum delay		72
maximum delay between two			76
maximum sum of two or more
delays	75
pulse control	57
timing constraints		72
wire delays	52

RECOVERY keyword		65
recovery timing check		65
RECREM keyword	67
reject limit 46
relational operators	33
REMOVAL keyword		66

replacing values in existing delays 44 RETAIN keyword 49

January 2001

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SDF Annotator Guide

SCALE_FACTORS keyword							21, 22
example			22
SCALE_TYPE keyword						21, 22
example			22
scaling operations					21, 22
scaling timing data					14
example			14
SCOND keyword				64, 68
SDF Annotator				10
errors		86
example call				14
restrictions 94
	COND keyword					95
	edge identifiers					96
	escape identifier					97
	multiple delay limitations 96
	PATHPULSE limitation						95
	revert to origianl timing						95
	TIMESCALE keyword						95
system task				12
SDF file		12
cell entries			41
comments			33
concepts			30
delay entries				83, 84
example			38, 82
format		83, 84
header 39
hierarchical design						31
use of characters 32
SDF-specific plus options 85
SDFVERSION keyword						40
SDPD	84
SETUP keyword				62
SETUPHOLD keyword						64
example			64
signal
clock event versus port signals								74
defining a clock					80
duration between clock edges								69
input applied during intended circuit
		operation			77
output applied during intended circuit
		operation			78
single-source nets					50
SITD	50, 53
SKEW keyword				68
SKEWCONSTRAINT keyword							74

SLACK keyword		79
SUM keyword 75
example	76
syntax
conventions		8
delays	43

TEMPERATURE keyword				41
time scale
SDF default	95
Verilog-XL default		95
time scales
synchronizing	93
time scaling 21
TIMESCALE keyword		41
timing
analyzing behavior for a circuit 77, 78,
80
retaining port values			49
timing checks
ARRIVAL 77
DEPARTURE	78
DIFF 76
disabling 90
HOLD 63
NOCHANGE	71
PATHCONSTRAINT			72
PERIOD 70
PERIODCONSTRAINT				74
RECOVERY	65
REMOVAL 66
SETUP 62
SETUPHOLD	64
SKEW 68
SKEWCONSTRAINT				74
SLACK 79
SUM 75
WAVEFORM	80
WIDTH 69
TIMINGCHECK keyword				60
COND keyword restriction					95
example 83
TIMINGENV keyword		72
transport delays	89
TURNOFF_DELAY keyword					23
example 23
typical
delay values	13

January 2001

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SDF Annotator Guide

MTM keyword 21 time scale 14 time scaling 22

unary operators 33

VENDOR keyword	40
Verifault-XL
path pulse control		57
SDF file header keywords			40
SDF keywords	36
Verilog-XL
path pulse control		57
SDF file header keywords			40
SDF keywords	35
SDF-specific plus options			85
Verilog-XL restrictions		94
VERSION keyword	40
VOLTAGE keyword	40

warning suppression		87, 88
WAVEFORM keyword		80
WIDTH keyword	69
wildcard character	42
wire path delays	52

zero-delay timing information 94

January 2001

123

Product Version 3.2

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