SDF Annotator Guide

Annotating with Verilog-XL and Verifault-XL

Table 4-1 Plus Options that Control the SDF Annotator

See “SDF Keywords for Verilog-XL” on page 35 for the OVI SDF standard keywords that Verilog-XL uses.

See “SDF Keywords for Verifault-XL” on page 36 for the OVI SDF standard keywords that Verifault-XL uses.

+sdf_cputime

The +sdf_cputime plus option logs the number of central processing unit (CPU) seconds that it takes to complete the annotation. The CPU time is written to the log file.

+sdf_error_info

The +sdf_error_info plus option displays PLI error messages.

Note: SDF Annotator errors are classified as fatal and non-fatal errors. Fatal errors cause the

SDF Annotator to stop. Non-fatal errors do not stop the SDF Annotator, but cause it to skip the action that caused the error. An example of a non-fatal error is when a condition specified in the SDF file cannot be matched in the Verilog description.

SDF Annotator Guide

Annotating with Verilog-XL and Verifault-XL

+sdf_file<filename>

The +sdf_file plus option with a corresponding appended file name (no space in between) specifies the SDF file that the SDF Annotator uses. This plus option overrides the file specified as an argument to the $sdf_annotate system task.

+sdf_ign_timing_edge

Note: This option is applicable for Verilog-XL only.

The +sdf_ign_timing_edge plus option annotates the last edge without any extra overheads for SETUP, HOLD and SETUPHOLD. By default, Verilog-XL generates an error message during annotation if the verilog file contains a timing check without an edge and the sdf file contains an edge. To facilitate annotation, you can use the +sdf_ign_timing_edge plus option. Consider the example given below.

Verilog File:

$setup(data, clk, 2); $hold(clk, data, 1);

SDF File:

(SETUP (posedge data) clk (3)) (SETUP (negedge data) clk (3)) (HOLD (posedge data) clk (2)) (HOLD (negedge data) clk (2))

In this example, the timing check signal data does not contain an edge in the Verilog file but contains both a posedge and a negedge in the SDF file. Using the +sdf_ign_timing_edge plus option, the timing check signal data will first be annotated with a posedge and then a negedge. In effect, the last edge defined is annotated.

+sdf_nocheck_ celltype

The +sdf_nocheck_celltype plus option disables celltype validation between the SDF Annotator and the Verilog description. By default, the SDF Annotator validates the type specified in the CELLTYPE construct against the type of the cell instance that is specified in the INSTANCE keyword construct.

+sdf_no_errors

The +sdf_noerrors plus option disables error messages from the SDF Annotator.

SDF Annotator Guide

Annotating with Verilog-XL and Verifault-XL

+sdf_nomsrc_int

If you have no multisource interconnect transport delays (MITDs) in the design, the

+sdf_nomsrc_int plus option increases performance and reduces memory consumption by not maintaining information about the various interconnects that map to the same port. If you have multiple interconnects in the design that map to the same input port, the SDF

Annotator must resolve these delays using a resolution function prior to annotating the port.

The SDF Annotator provides three resolution functions (AVERAGE, MAXIMUM, and MINIMUM). For the SDF Annotator to correctly resolve the delays, it must maintain the interconnect information until the end of annotation.

+sdf_no_warnings

The +sdf_no_warnings plus option disables warning messages from the SDF Annotator.

+sdf_split_two_timing_check +sdf_splitvlog_splitsuh +sdf_splitvlog_splitrecrem

Note: These options are applicable for Verilog-XL only.

SDF Annotator attempts to match the one-timing checks (SETUP, HOLD, REMOVAL, and RECOVERY) to their corresponding one-timing checks in the Verilog source. If no match is found, then the SDF annotator splits the two-timing checks ($setuphold and $recrem) in the Verilog source into corresponding one-timing checks and attempts to match. For example, $setuphold is split into $setup and $hold and then matched to SETUP and HOLD.

You can split SDF two-timing checks (SETUPHOLD and RECREM) using the +sdf_split_two_timing_check plus option into their corresponding one-timing checks. The conditions specified with SETUPHOLD and RECREM are ignored after the split.

If you have used +sdf_split_two_timing_check plus option and no two-timing checks are found, the SDF Annotator reports errors in terms of corresponding split timing checks.

The options +sdf_splitvlog_splitsuh and +sdf_splitvlog_splitrecrem can be used to perform splitting of SETUPHOLD only and RECREM only respectively.

+sdf_verbose

The +sdf_verbose plus option writes the following detailed information about the annotation process to the SDF Annotator’s log file: