Additional Plus Options that Control the SDF Annotator

Plus Option

Description

+annotate_any_time

Allows SDF backannotation to occur at times other

than time 0.

+maxdelays

Selects the maximum delay.

+mindelays

Selects the minimum delay.

+multisource_int_delays

(Verilog-XL only) Affecting only nets with more than

one source, provides transport delays with full pulse

control and the ability to specify unique source/load

delays. MIPDs are inserted on all single-source

nets. Using the +multisource_int_delays plus

option with the +transport_int_delays plus

option provides transport delays with full pulse

control for interconnect delays with one or more

sources and unique source/load delays for such

nets.

January 2001

89

Product Version 3.2

Plus Option

Description

+neg_tchk

(Verilog-XL only) The +neg_tchk plus option

enables negative timing check arguments in the

$recrem and $setuphold timing checks.

When you do not use the +neg_tchk plus option,

any limits that are negative, either in the description

or annotation, are set to 0, and a warning is issued.

You can specify negative time arguments for

$recrem only if you are specifying values for both

the <recovery_limit> and

<removal_limit> arguments. When either the

<recovery_limit> or <removal_limit>

argument is negative, the sum of the two limits must

be 0 or greater.

+no_pulse_int_backanno

(Verilog-XL only) Prevents PLI annotation of pulse

limits for interconnect delays. Only one warning

message is issued on the first attempt.

+notimingchecks

Disables all timing checks. When you disable timing

checks, processing speed improves and the circuit

data structure requires less memory.

For Verifault-XL, this is set by default.

Note: Module path delays remain active.

+pulse_e/n and +pulse_r/m

(Verilog-XL only) The +pulse_e/n and

+pulse_r/m plus options control the way in which

pulse rejection and pulse error limits are annotated

to module paths. If you do not specify values for

these limits in an IOPATH construct, the SDF

Annotator applies the percentages specified in

these plus options to calculate a pulse reject and

error limit to annotate. Also, if you do not specify

these plus options, then the SDF Annotator defaults

to 100% for both the reject and error percentages.

See the Verilog-XL Reference for more

information about pulse rejection for module paths.

January 2001

90

Product Version 3.2