SDF Annotator Guide

2

Using the Configuration File

This chapter describes the following:

■Understanding the Configuration File on page 16

■Configuration File Keyword Syntax on page 17

Understanding the Configuration File

The configuration file allows you to filter timing data in the SDF file before the data is annotated to a Verilog family tool using the SDF Annotator configuration file. If you do not use a configuration file, the SDF Annotator uses default settings for annotation, and you can skip this chapter. You can do the following using the configuration file.

■Map or ignore timing constructs from the SDF file to the Verilog HDL description

■Select multiple timing specifications

■Select minimum, typical, or maximum delays values

■Specify scaling operations

■Determine turn-off delays

■Specify delay data for a specific type of module

Sample Configuration File

Many of the configuration file keywords are shown in the following example. If the SDF Annotator finds conflicting keywords, it uses the last specified keyword.

Note: Keywords must be in uppercase letters. Blank lines are not allowed.

Configuration File Keyword Syntax

This section lists the keywords you can specify in the configuration file.

Timing Keywords

The following keywords have only one option (IGNORE), which specify whether the SDF Annotator ignores the constructs in the SDF file. See Chapter 3, “Using the SDF File” for information about using these keywords in the SDF file.

■DEVICE = IGNORE;

■HOLD = IGNORE;

■INTERCONNECT = IGNORE;

■IOPATH = IGNORE;

■NETDELAY = IGNORE;

■NOCHANGE = IGNORE;

■PATHPULSE = IGNORE;

■PATHPULSEPERCENT = IGNORE;

■PERIOD = IGNORE;

■PORT = IGNORE;

■RECOVERY = IGNORE;

■SETUP = IGNORE;

■SETUPHOLD = IGNORE;

■SKEW = IGNORE;

■WIDTH = IGNORE;

SDF Annotator Guide

Using the Configuration File

Default Mapping for Verilog-XL

In Verilog-XL, if you do not specify a mapping for a timing keyword, the SDF Annotator uses the default mapping for that keyword as shown in Table 2-1 on page 18.

Table 2-1 Default mapping for Verilog-XL

a.Module Input Port Delay

b.Single-Source Interconnect Transport Delay

c.Multisource Interconnect Transport Delay

Default Mapping for Verifault-XL

In Verifault-XL, if you do not specify a mapping for a timing keyword, the SDF Annotator uses the default mapping for that keyword as shown in Table 2-2 on page 19.

SDF Annotator Guide

Using the Configuration File

Table 2-2 Default Mapping for Verifault-XL

Default Mapping for Veritime

In Veritime, if you do not specify a mapping for a timing keyword, the SDF Annotator uses the default mapping for that keyword as shown in Table 2-3 on page 19.

Table 2-3 Default Mapping for Veritime