SDF Annotator Guide

Annotating with Verilog-XL and Verifault-XL

Improving SDF Annotator Performance and Memory Use

Annotation is an important and time consuming process for simulating designs. Because many annotation operations are design dependant, you can optimize the annotation process to achieve maximum performance The SDF Annotator Version 2.0 has significantly improved its performance from the previous version. The first table summarizes some of the

SDF Annotator Guide

Annotating with Verilog-XL and Verifault-XL

performance improvements. The first table shows the sample specifications. The second table describes the performance improvements

Note: The information described in this section is deliberately broad and generic. Requirements for your specific design may dictate procedures slightly different from those described here.

Removing Module Mapping

If your design does not require module mapping, you can achieve a significant improvement in annotation performance by removing MODULE keyword constructs.

You can map timing constructs that do not correspond exactly to the design specification.

However, for every cell encountered, the SDF Annotator determines if the cell is mapped and if it is, performs a second check to determine the timing construct to which timing information is mapped. In the configuration file, annotation information is retained in memory by the SDF Annotator in an internal data structure. The retained information can get large enough to cause swapping and affect performance.

Disabling Multisource Interconnect Timing Resolution

You should use the +sdf_nomsrc_int plus option only when you do not need to resolve between multiple timing specifications. If you know that multisource interconnects do not exist

SDF Annotator Guide

Annotating with Verilog-XL and Verifault-XL

in the design and are using MIPDs to annotate interconnect delays, you can significantly improve performance by using the +sdf_nomsrc_int plus option.

An interconnect delay in the SDF file can be mapped to a MIPD, SITD, or MITD. When a multisource interconnect delay is mapped to a MIPD, the SDF Annotator resolves it using average, maximum, and minimum values. The annotator retains interconnect information in cache memory to annotate timing information into the design after processing the SDF file. The +sdf_nomsrc_int plus option disables the retention of interconnect information.

Using Pre-scaled Delays

You can specify scaling operations for the timing information in the SDF file before the delays are annotated into Verilog-XL. However, you can improve performance if your design contains prescaled delays. Because the SDF Annotator must perform floating point operations for each delay value, scaling can affect the performance of the SDF Annotator.

Synchronizing Time Scales

When the time scales for the Verilog-XL description and the SDF file are the same, you can improve performance. If the time scales in the SDF File and the Verilog description are different, the SDF Annotator performs a multiplication operation for each delay to obtain the correct scaling.

Synchronizing Precision

When the precision of the time (degree of accuracy) for the Verilog-XL description and the SDF file are the same, you can improve performance. If the precision is different, the SDF Annotator performs rounding operations.

Disabling Cell Type Verification

The CELLTYPE keyword specifies the type of cell that contains the timing information in the SDF file. The SDF Annotator verifies that a type of cell in the SDF file corresponds to the type of cell in the Verilog-XL description. If there are many cells, the verification can be time consuming. The +sdf_nocheck_celltype plus option disables this verification.

Note: You should use the +sdf_nocheck_celltype plus option only when you are confident that the syntax of the SDF file is correct.

This check is useful when one of the cells does not match, because the SDF Annotator will not attempt to annotate any of the delays in the invalid cell