SDF Annotator Guide

Preface

This preface describes the following:

■About This Guide on page 7

■Other Sources of Information on page 8

■Syntax Conventions on page 8

About This Guide

This guide describes the Standard Delay Format (SDF) Annotator™ , which facilitates the exchange of timing data between an SDF file and a Verilog family tool. The SDF Annotator uses the SDF file as input for the annotation process. This guide assumes that you are familiar with one or more of the Verilog family tools.

Finding Information in This Guide

This guide describes the SDF Annotator and is organized as follows:

Chapter 1, "Using the SDF Annotator" describes the SDF Annotator and how to call it from the Verilog Hardware Design Language (HDL).

Chapter 2, "Using the Configuration File" describes the optional configuration file, which lets you filter timing data in the SDF file before the data is annotated to the Verilog family tool. If you donot use a configuration file, you can skip this chapter.

Chapter 3, "Using the SDF File" describes the SDF file, which stores timing data generated by the Verilog family tool. It also describes the conventions and keywords for the SDF file, including the keywords that are used by various Verilog family tools.

Chapter 4, "Annotating with Verilog-XL and Verifault-XL" describes the SDF-specific plus options you can specify on the Verilog-XL command line. It also describes the restrictions you have between the SDF Annotator and Verilog®-XL.

Appendix A, “SDF Annotator Error and Warning Messages” lists the Error and Warning messages that the SDF Annotator issues.