material1 / different / Chung-Yu Wu - Analog Circuit Design

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§17-2 Phase Detectors in PLLs

Three categories: 1. Analog phase detectors (PDs) or multipliers:

Rely on the DC component when multiplying two sinusoidal waveforms of the same frequency.

2. Sequential circuits (e.g. EXOR and Flip-Flop PDs):

Operate on the information contained in the zero-crossings of the input signal to aid acquisition when the loop is out of lock. Also a sequential circuit actually.

3. Phase-frequency detector:

Provide a frequency sensitive signal to aid acquisition when the loop is out of lock. Also a sequential circuits actually.

§17-2.1 Multiplier PD

Vpd =KMEinsin(ω1t+θ1)Eosccos(ω2t+θ2)

=KM Ein Eosc {sin[(ω1-ω2)t+θ1-θ2]+sin[(ω1+ω2)t+θ1+θ2]} 2

At phase lock, ω1=ω2

=> Vpd= KM Ein Eosc [sin(θ1-θ2)+sin(2ωt+θ1+θ2)] 2

After the lowpass filter, we have

*The multiplier PD is especially useful in applications where the reference frequency is too high and where the loop bandwidth is sufficiently narrow so that the filtering of the undesired components can be effective.

*The loop could lock to harmonics of the input signal.

=>False lock

* ω1=ω2 is required.

§17-2.2 EXOR PD

B

C=A B

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(c)

*when A(Vin) and B(Vosc) are 90° out of phase, the output Vpd(c ) has ω=2ωin and 50% duty cycle. This is a reference point. Vpd θd for 0o<θd<180°.

*False lock could occur

*ω1=ω2 is required.

§17-2.3 Flip-Flop PD

C

*The average value of Vpd or C has the shape of a saw tooth, with a linear range of a full cycle.

*At the center of the linear range of Vpd average, the most important harmonic is situated at the fundamental of the reference frequency as compared to the twice of reference frequency in the EXOR PD.

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Fundamental

2nd Harmonic

§17-2.4 Charge-pump PD

1.Desirable features: 1. It does not exhibit false lock.

2.Vin and Vosc are exactly in phase when the loops in lock.

3.The PLL attains lock quickly even when ωin is quite different from ωfr.

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3. Design Considerations:

(1)Choose Ich based on practical consideration like power dissipation and speed.

(2)ωo is chosen according to the desired transient settling-time constant τpll as

ωo= τ1

pll

(3)C1 is chosen from the equation of ωo whereas R is chosen using the equation of Q. The chosen Q value is slightly less than what is eventually desired. R↑ => Q↓

(4)Add C2 to minimize glitches.

C2 => Q↑ => chosen Q value is smaller => Exact Q.

=> Ηlp(s)=1+ SRCR 2 + SC1 1

4.Phase/Frequency detector (PFD)

*The most common sequential phase detector is the PFD.

*Asynchronous sequential logic circuit.

*4 NOR-type RS flip-flops.

*Can also be realized in NAND gates.

Pu Pd

set3 set4

* Basic operating principle:

Assume the PLL is in lock with Vin leading Vosc

Initial conditions: Pu=0, Pd=0, Pu-dsbl=0, Pd-dsbl=0, Reset=0 Vin=0, Vosc=0

inputs: 1001

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Vin→1 => Pu=1 => Charge pumping starts and Vlp ↑=> ωosc↑ Vosc→1 => Reset nor gate inputs: 0001→0000 => Reset 0→1

=> Pu=0 and Pd=0 after one gate-delay ; Pd 0→1→0 Pu-dsbl=1 and Pd-dsbl=1 after two gate-delays.

=> Reset 1→0 after one gate-delay of Pu-dsbl→1 and Pd-dsbl→1 or after three gate-delays of Vosc→1.

=> Κeeping Pu=0 and Pd=0 => Νο charge pumping.

It is only when Vin 1→0 => FF3 is reset and Pu-dsbl=0 Vosc 1→0 => FF4 is reset and Pd-dsbl=0

* The waveforms of a PFD when Vin is at a higher frequency than Vosc.

Vin

Vosc

Pu

Pd

Pu-dsbl

Pd-dsbl

ωin>ωosc => Pu=1 => Charge pumping to increase ωosc until lock is achieved.

* Transfer characteristic of a charge-pumping PFD

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§17-3 Loop Filters and Loop Gains

§17-3.1 First-order PLL with zero-order loop filter

Loop gain of the feedback structure with φin(s) and Vcntl(s)

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§17-3.4 Third-order type-2 charge-pump PLL

§17-4 Voltage-Controlled Oscillators (VCOs)

Basic VCO specifications/requirements: 1. phase stability:

The output spectrum of the VCO should approximate as good as possible the theoretical Dirac-impulse of a single sine wave, i.e. low phase noise.

The definition of phase noise:

VCO output

2. Electrical tuning range

The VCO must be able to cover the complete required frequency band of the application, including initial frequency offsets due to process variations.

3. Tuning linearity

To simplify the design of the PLL, the VCO gain Kosc should be

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constant.

4. Frequency pushing (MHz/V)

The dependency of the center frequency on the power supply voltage.

5. Frequency pulling

The dependence of the center frequency

6. Low cost

§17-4.1 Relaxation oscillator as VCO

*Multivibrator-based nonlinear oscillator.

*fosc~in the order of a few 100 MHz

*In CMOS, phase noise value of -90dBc/Hz at 500KHz offset.

Ref.: IEEE JSSC, vol.23, pp.1386-1393, Dec. 1988.

§17-4.2 Ring oscillator as VCO

* Tosc=2n•Td n: number of inverters; Td: one inverter delay.

*Tuning: varying the current of the inverters.

*High phase noise: switching action introduces a lot of disturbances.

* Power consumption ↑ linearly => phase noise↓ * Typical phase noise:

-94dBc/Hz at 1 MHz offset from a 2.2GHz carrier. -83dBc/Hz at 100 KHz offset from a 900MHz carrier.

*Circuit structure

1.Three-stage ring oscillator inverter

2.Differential two-stage ring oscillator