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Национальный исследовательский университет «МИЭТ»

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Chung-Yu Wu - Analog Circuit Design

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13-25

CHUNG-YU WU

Table II Comparison of the proposed A/D converter with the previous ratio-independent A/D converters [4.4]-[4.5].

A/D converters
Performance	[4.4]	[4.5]	This work
Performance

Resolution
(bits)	12	8	14
(bits)

Absolute
INL (LSB)	<= 1.5	<= 0.5	<= 1
INL (LSB)

OP amp dc
Gain (dB)	92	84	60
Gain (dB)

Clock cycles
for n bits	6n	3n	7n
for n bits

Sampling rate
(KHz)	8	8	10
(KHz)

Power dissipation
(mW)	17	-	50
(mW)

13-26

CHUNG-YU WU

§13-5 Full Flash (Parallel)

*Need 2N-1 comparators for N bits.

*Need 2N-1 Resister (R) tapes for N bits.

*S/H usually combined with comparators. (No op amp is required) ? Large no. of analog elements.

? Large chip area power consumption.

Full-flash A/D converter

VIN

VREF+

2N-1

2N-2

comparator

Clock generator

2N-1

2N-2

Encoder

2N-1 to N binary code

Latch

VREF-

Output registor & buffer

bN-1

bN-2 bN-3

b2 b1 b0

13-27

CHUNG-YU WU

§13-5.1 MOS Flash ADC's

Ref.: IEEE JSSC, vol. sc-14, pp. 926-932, Dec. 1979.

CMOS/SOS 6 bit 20 MHz ADC.

6-BIT BINARY OUTPUT

Block diagram of A/D converter chip.

High speed autozeroed CMOS/SOS comparator.

13-28

CHUNG-YU WU

Discrete and distributed reference ladder models

Ccomp £ 0.05 pF, RTAP = 20W

Z(w)

³50,000 (< 10,000, don't work)

R TAP

Reference ladder leading as a function of input voltage

(|Z|(W) /RTAP = 500)

Effect of loading ratio on reference ladder output.

13-29

CHUNG-YU WU

Major source of error is the loading of the reference resistor ladder by the

comparator bank.

Resistor ladder loading errors are of two types:

(1)"Transient error" associated with instantaneous ladder loading during a single measurement;

(2)Long-term "recovery error" associated with errors at a new input level after the ladder has been loaded for a long period by inputs at another level.

If the capacitor bypassing is performed at the externally accessable ladder

midpoint tap,

Þtransient impedance ¯ by a factor of more than 4.

ÞWorst-case static loading which can't be bypassed makes recovery errors

the significant error source.

* All the errors considered above are of this type.

Typical 6-bit A/D converter Performance:
Power dissipation at 15 MHz clock, 20 pF/output.
	5V	8V
convert mode	50mW	145mW
Tracking mode	45mW	130mW
3.2V reference	9mW	9mW
Input Cap.	8 pF	8 pF
Recom. Vref	3.2V	6.4V
On-chip Zener Reference	3.2V	6.4V
Input voltage source resistance	75W	75W
Accuracy 15MHz	1 LSB	1 LSB
	2	2
20MHz	---	1 LSB
25MHz	---	1.5 LSB

13-30

CHUNG-YU WU

§13-5.2 7-Bit CMOS Flash ADC for Video Applications

Ref.: IEEE J. Solid-State Circuits, vol. sc-21, pp. 436-440, June, 1986

Overall schematic:

				D-Type
				Output
VREF		Comparator		Latch
VREF				Overflow
TOP
TOP		R/2 Banks Latches
		R/2 Banks Latches
		127
		R		D6
				D5
		R
		64	128 to	D4
		R/2	7 bit	D4
Mid		R/2	7 bit
Mid			Encoder
Decouple			Logic
		R/2	Logic	D3
	Cext	R/2		D3
	Cext
Capacitor		R		D2
Bypassing		R
Bypassing
				D1
		R
		0
VREF		R/2		D0
VREF		R/2
Bottom
Analog
Input

Clock Buffer

R:Polysilicon resistor, 10 Ω / bit 2μm Poly-gate VLSI CMOS Overall ship area: 135×142 mil2

13-31

CHUNG-YU WU

Comparator and the primary latch

+VDD

	Load	OUTPUT
	OUTPUT Bias	OUTPUT
	OUTPUT Bias

	Q10		Q11	Q12		Q13
						Q14
Q16		Q3
Vbias		Q3			Q4	Vbias
Vbias

			Q5	Q6		Reference
Analog			Q5	Q6		Input
						Input

Input	Q1					Q2
	Q1					Q2
		Latch	Q8	Q9	Latch
		Latch	Q8	Q9
I2Bias		IBias				I2Bias
I2Bias		IBias		Q7
				Q7		Q15
						Q15
				-VSS

Gain: 18dB	Q10, Q13: Operated in linear region
Bandwidth: 40 MHz	with on-chip low-power
	OP AMP and reference
	loop.
	Þ Ro¯, fu-.
Q5,Q6: Positive feedback to	Q11, Q12: To limit the output swing
form latch.	and	enable		the
	comparator		to recover
	much	faster	from	the
	latched state.
The secondary latch is of the hysteresis type, because

(1)it can convert the limited logic swing of the primary latch to correct CMOS logic levels.

(2)it can reduce the amount of hysteresis to ~ 100mV by setting "Latch"

13-32

CHUNG-YU WU

signal to High. Thus the latch always experiences an overdrive of 100 mV.

ÞAvoid ambiguous state and increase the resolution time of the comparators.

ÞReduce metastability error probability

Performance characteristics:
7-bit inherently monotonic
Accuracy: differential and integral	± 0.5 LSB.
Analog bandwidth	: -3dB 42 MHz; - 1 LSB 5 MHz
	2
Maximum sample rate	: > 22 MSPS, 30 MSPS typically
VDD	: 5V ± 0.5V
Input range	: 1.5V~3.5V
Power consumption (25MSPS)	: 350 mW
Temp. range	: - 40 o C to + 85 o C

§13-5.3 CMOS 20 MS/S (Maga Samples /sec) 7-bit Flash ADC

Ref.: ISSCC 84, PP. 56-57, 315.

Nonsampling amplifier:

	φ1	S5
		S5
φ1		VDD	VDD
φ1		VDD
S1	CA		φA
			S7	LATCH
S2
φ1				Sampling
				Clock
	φ2	S6
φ2	φ2	VDD	VDD
φ2
S3			φB
			φB
			S8
S4	CB
S4
φ2

* Higher operating. frequency

13-33

CHUNG-YU WU

§13-5.4 Metastability error

Ref.: IEEE JSSC, vol. 31, pp. 1132-1140, Aug. 1996, 7-b 80-MHz flash ADC

Metastability error: occurs in ADCs when undefined comparator outputs pass through the encoder to the converter output bits.

VA < V REFi+1	0			0	VA < VREFi+1
	0			0	VA < VREFi+1
		i+1

	0		i+1	0				Metastable
	0		i+1	0

	1	i	i	X		VA	~	VREFi state
	1	i	i	X
	1		i-1	1
	1		i-1	1
VA > V REF	1			1	VA > VREFi-1

Thermometer code with	Thermometer code with
valid comparator outputs	metastable comparator

*Metastability error rate is an exponential function of the sampling frequency.

*It is nearly independent of the input frequency.

*At 70-MHz sampling frequeny, the metastability error rate is ~ 10-7 errors/cycle.

Þ7 errors per second

*Can be improved to < 10-12 errors/cycle.

13-34

CHUNG-YU WU

§13-6 Two-Step Flash or Subranging ADC

Conventional two-step A/D converter:

					+
VIN	SAMPLE	COARSE		-	FINE
VIN	&	FLASH	DAC	-	FLASH
	&	FLASH	DAC		FLASH
	HOLD	ADC			ADC
					ANALOG
					ADDITION

LATCH

DIGITAL

OUTPUT

Two-step A/D converter with single resister ladder:

	Vin			VIN
MSB'S	Vin
MSB'S
TGS2		SAMPLE	TGS	SAMPLE
TGS2		SAMPLE
COARSE	TGC16	VREF		LSB'S
COMPARATOR			15	LSB'S
NO. 16		R16
COARSE	TGC15	R16
COARSE	TGC15
COMPARATOR			15
NO. 15			15
COARSE	TGC14	R15
COMPARATOR	TGC14
COMPARATOR
NO. 14			15	FC #15
				FC #15

"COARSE"		R14		FC #14
"COARSE"				FC #14
DECODER
/ENCODER
				FINE
		R3	15	DECODER
COARSE	TGC2	R3		/ENCODER
	TGC2			/ENCODER

COMPARATOR
NO. 2		R2	15
COARSE	TGC1	R2	15
	TGC1

COMPARATOR
NO. 1			15
		R1	15	FC #2
	CLEAR	R1		FC #2
	CLEAR
		VREF		FC #1
		VREF
				"FINE"
				COMPARATOR

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