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5. Practical folders:

(a)

(b)

Fig. 7 (a) The contribution of the fifth amplifier goes unused.

(b)This redundancy is used to reduce the number of preamplifiers

*Vx1 and Vx2 are fixed voltages generated by a single preamplifier shared by all folders.

*Power dissipation ¯.

6.Interpolation with current-mode folder signals

Fig. 8. Interpolation can be used to eliminate half or more of the folder blocks

Fig. 9. Interpolation with current-mode folder signals. A current split-in- four block is shown on the right.

* The number of folders ¯. Þ 16 ® 8

* Problems: (1) It adds an extra node to the signal path, reducing the bandwidth of the folder circuit.

(2) It does not work readily at low power supply voltages.

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* Improved circuit:

Merge the current division within the folder.

Fig. 10. The folder is modified to include current division. The modified amplifier is on the right. A block diagram for a modified folder is also shown.

*Fast operation and low-voltage operation.

7.Comparator design

(1) First stage:

Fig. 12. The comparator core (a) tracking and (b) latching.

*Current-input voltage-output comparator.

*Resistor load.

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*Advantages:

(a)Currents are summed to drive the latch (i.e. IinL + IinR) Þ The input signal has very little effect after latching begins.

(b)IinL and IinR always flow from tracking to latching Þ The folders are little disturbed.

*Need the second-stage buffer and latch.

(2)Second stage:

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(3) Third stage to reduce metastability errors:

SR latch

8.Complete ADC block diagram

The sync block: To suppress the delay mismatch between the coarse ADC and the rest of the circuitry (i.e. the fine converter)

Fig. 16. (a) ADC block diagram with detail of coarse ADC. (b) Coarse ADC waveforms

*MSB-Lo and MSB-Hi are offset by 18 Fs at either side of the MSB transition voltage.

*If MSB-1 = 0, MSB = MSB - Lo If MSB-1 = 1, MSB = MSB - Hi

* Can tolerate a relative offset of up to ±

1 Fs.

 

8

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9. Measurement results:

Fig. 18. SNDR versus input frequency at 400 Msample/s

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Fig. 19. Die photo

§13-9 Summary

 

16

(Bits)

15

14

Resolution

13

 

 

12

11

10

9

8

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[5]

[7]

[8]

[4]

[3]

[2]

[6]

[9]

[1]

 

 

 

 

 

 

 

 

 

10

30

50

190

210

320

330

600

620

 

 

 

 

Conversion Rate (KHz)

 

 

 

 

 

 

 

Resolution versus sampling frequency plot of

 

 

 

 

 

recently reported CMOS audio A/D converters

 

YU-CHUNG

 

 

 

 

 

 

 

 

 

81-13

 

 

 

 

 

 

 

 

WU

 

Resolution (bits)

13

12

11

10

9

8

7

6

5

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*[30] (166mW), T3

 

 

 

 

 

 

CHUNG-YU WU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(200mW, T2)

 

 

 

*: 5V

 

T1: Full Flash

[15]

[33] (335mW), T3

 

 

 

 

: 3.3V

 

T2: Two-step flash or Subranging

 

*

*

 

 

 

 

 

T3: Pipelining

 

 

 

 

 

: 3V

 

 

 

[24], T3

[34] (250mW), T3

 

 

 

: 2V

 

T4: Interpolating

 

 

 

 

(135mW)

 

 

 

 

 

 

T5: Folding

 

 

 

 

 

: 2.5v

 

 

 

(35mW) (135mW)

(85mW)

 

 

 

 

T6: Parallel

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T3, [20] [18], T2

T3 & T6,

(900mW)

 

 

 

 

T7: Over sampling

 

 

 

[21]

[19], T3

 

 

 

*

*

 

[35] (195mW),*T2

*

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[17]

[36]

[22]

 

 

 

 

 

(350mW,

 

 

 

 

 

T2,

T2,

 

 

 

 

 

T2)

 

T4&T5

T5

 

 

(75mW)

(135mW)

 

 

 

 

 

 

 

 

 

 

(76mW, T6)

(135mW)

(80mW)

(1.1W, T3)

(225mW)

 

 

 

 

 

 

 

 

 

 

[11]

[23]

[25]

[10]

[29], T5

*

*

*

*

*

 

 

 

[16]

[13]

[14]

 

 

 

 

 

(200mW, T2)

(250mW, T1)

(600mW, T2)

 

T4

T1

T1

T3&T7

 

 

 

T1, [28]*

 

 

 

(110mW)

 

 

 

(160mW)

(190mW)

(225mW)

 

 

 

(307mW)

[26]

 

 

 

[27]

[32]

[37]

 

 

 

 

 

 

 

 

*[12]

 

 

[31]

 

 

 

(400mW, T1)

 

 

(200mW)

 

 

 

 

 

 

T4&T5

10

20

30

40

50

60

70

80

90

125

175

200

300

400

500

Conversion Rate (MHz)

Resolution versus sampling frequency plot of recently reported CMOS video A/D converters

YU-CHUNG

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WU

 

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[1]H. Ondera, T. Tateishi, and K. Tamaru, "A cyclic A/D converter that does not require ratiomatched components," IEEE J. Solid-State Circuits, vol. 23, pp. 152-158, Feb.1988.

[2]P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, " A ratio-independent algorithmic analog-to- digital conversion technique," IEEE J. Solid-state Circuits, vol. SC-19, pp.828-836, Dec. 1984.

[3]H. S. Lee, " A 12-b 600Ks/s digitally self-calibrated pipelined algorithmic ADC," IEEE J. Solid-Dtate Circuits, vol. 29, no. 4, pp. 509-515, Apr. 1994.

[4]Shu-Yuan Chin and Chung-Yu Wu, "A ratio-independent and gain insensitive algorithmic analog-to-digital converter," 1993 IEEE International Symp. on Circuits and Systems, Chicago, U.S.A., pp.1200-1203, May 3-6, 1993.

[5]M. de Wit, K. S. Tan, R. K. Hester, " A low-power 12-b analog-to-digital converter with onchip precision trimming," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 455-461, Apr. 1993.

[6]G. Yin, F. Stubbe, and W. Sansen, " A16-b 320-KHz CMOS A/D converter using two-stage thrid-order ΣΔ noise shaping," IEEE J. Solid-State Circuits, vol. 28, no. 6, pp. 640-647, June 1993.

[7]B. Ginetti, P. G. A. Jespers and A. Vandemeulebroecke, " A CMOS 13-b cyclic RSD A/D converter," J. Solid-State Circuits, vol.27, no. 7, pp.957-964, July 1992.

[8]H. S. Lee, D. A. Hodeges, and P. R. Gray, " A self calibrating 15-bit CMOS A/D converter," IEEE J. Solid-State Circuits, vol. SC-19, pp.813-819, Dec. 1984.

[9]T. Ritoniemi et al, " A stereo audio sigma-delta A/D converter," IEEE J. Solid-State Circuits, vol. 29, no. 12, pp.1514-1523, Dec.1994.

[10]C. S. G. Conroy, D. W. Cline, and P. R. Gray, " An 8-b 85-Ms/s parallel pipeline A/D converter in 1-um CMOS," IEEE J. Solid-State Circuits, vol.28, no. 4, pp.447-454, Apr. 1993.

[11]Shu-Yuan Chin and Chung-Yu Wu, "A 3 V 8-bit 50-Msample/s A/D Converter," submitted to IEEE J. Solid-State Circuits.

[12]H. Reyhani and P. quinlan, " A 5V 6-b 80Ms/s BiCMOS flash ADC," IEEE J. Solid-State Circuits, vol. IEEE J. Solid-State Circuits, vol. 29, no. 8, pp.873-878, Aug. 1994.

[13]M. J. M. Pelgrom, A. C. J. V. Rens, M. Vertreg, and M. B. Dijkstra, " A 25-Ms/s 8-bit CMOS A/D converter for embedded application," IEEE J. Solid-State Circuits, vol.29, no. 8, pp.879886, Aug. 1994.

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[14]M. Ishikawa and T. Tsukahaara, "An 8-bit 50-Mhz CMOS A/D converter," IEEE J. SolidState Circuits, vol. 24, no. 12, pp. 1485-1491, Dec. 1989.

[15]B. Razavi and B. A. Wolley, "A 12-b 5-Msample/s two-step A/D converter," IEEE J. SolidState Circuits, vol. 29, no. 12, pp.1667-1678, Dec. 1992.

[16]A. G. F. Dingwall and V. Zazzu, " An 8-MHz CMOS subranging 8-bit A/D converter," IEEE J. Solid-State Circuits, vol. Sc-20, no. 6, pp. 1138-1143, Dec.1985.

[17]J. Doernberg, P. R. Gray and D. A. Hodges, " A 10-bit 5-Msample/s CMOS two-step flash ADC," IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 241-249, Apr.1989.

[18]M. Ito et al., " A 10bit 20 Ms/s 3V supply CMOS A/D converter," IEEE J. Solid-State Circuits, vol. 29, no. 12, pp.1531-1536, Dec. 1994.

[19]M. Yotsuyanagi, T. Etoh, and K. Hirata, " A 10-b 50-MHz pipelined CMOS A/D converter with S/H," IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 292-300, Mar. 1993.

[20]T. B. Cho, P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipelined A/D converter," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, Mar. 1995.

[21]K. Nakamura, M. Hotta, L. R. Carley, and D. J. Allstos, "An 85 mW, 10b, 40 Msample/s CMOS parallel-pipelined ADC," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 173-183, Mar. 1995.

[22]M. Yotsuyanagi et al., "A 2 V, 10 b, 20 Msample/s, mixed-mode subranging CMOS A/D converter," IEEE J. Solid-State Circuits, vol. 30, no. 12, pp.1533-1537, Dec. 1995.

[23]B. Nauta and A. G. W. Venes,"A 70-Ms/s 110mW 8-b CMOS folding and interpolating A/D converter," IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1302-1308, Dec. 1995.

[24]P. C. Yu and H. S. Lee, "A 2.5-V, 12-b, 5-Msample/s pipelined CMOS ADC," IEEE J. SolidState Circuits, vol. 31, no. 12, pp. 1854-1861, Dec. 1996.

[25]A. G. W. Venes and R. J. van de Plassche, "An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1846-1853, Dec. 1996.

[26]S. Tsukamoto et al., "A CMOS 6-b, 200 Msample/s, 3 V-supply A/D converter for PRML read channel LSI," IEEE J. Solid-State Circuits, vol.31, no. 11, pp. 1831-1836, Nov. 1996.

[27]R. Roover and M. S. J. Steyert, "A 175 Ms/s, 6 b, 160mW, 3.3 V CMOS A/D converter," IEEE J. Solid-State Circuits, vol.31, no. 7, pp. 938-944, July 1996.

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