12-9
CHUNG-YU WU
(3)Fast comparators with two amplifiers and a single latch.
*Usually, the speed of a latch is faster than that of a amplifier.
Two amplifiers share one latch.
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Vin |
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LATCH
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ψ 2 |
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* Operating clock waveforms
Vin-
12-11
CHUNG-YU WU
* φ2→1 inverters Q2-Q5 and Q3-Q6 are biased at their optimal points
C3 and C4 are also precharged such that any asymmetry between the two inverters is compensated by the slightly different bias voltages provided by C3 and C4.
loop gain of the latch 1.
* Vin+ Vin- : VC |
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VD |
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VinVin+ : VC |
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VD |
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12-13
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CHUNG-YU WU |
Performance: |
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Technology |
1.5 um CMOS |
Die size |
140 x 100 um2 |
Power supply |
+2.5 / -2.5 V |
Input dynamic range |
2.5 V |
Resolution |
8 bits, 1LSB=9.8 mV |
Sensitivity |
10.6 mV ( < 7 bits) |
Sampling rate |
65MHz |
Offset voltage |
3.3 mV |
Input capacitance |
30 fF |
13-1
CHUNG-YU WU
CH 13 CMOS Analog to Digital Converters (ADCs)
§13-1 Introduction
1. Functional block diagram of a A/D converter
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Control Logic
2.Ideal A/D Converter (ADC)
Vin ±Vx = Vref (b12−1 +b2 2−2 +××××+bN 2−N )
=Vref (b12N−1 +b2 2N−2 +××××+bN−121 + bN 20 )
2N
where Vin is the input analog voltage or current Vref is the reference voltage or current b1 … … . bN is the digital output
Vx is the tolerable input signal range
- 12 VLSB £Vx £ 12 VLSB
2-bit ADC: |
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Input-output transfer curve: |
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Bout |
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equivalent DAC transfer response |
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1 V |
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1 LSB) |
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1 V |
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ref |
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VLSB = |
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should remain less than 3/4 Vref |
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13-3
CHUNG-YU WU
4.Signal-to-Noise Ratio (SNR)
(1)Vin is a sawtooth of hight Vref (or a random signal uniformly distribut between 0 and Vref)
æ |
Vin(rms) ö |
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ÞSNR = 20logç |
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=20logç |
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= 20log2N =6.02 N dB |
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VLSB / |
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Q(rms) ø |
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(2) Vin is a sinusoidal waveform between 0 and Vref .
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ÞSNR = 20log |
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= 6.02 N +1.76dB |
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VLSB / |
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The above SNR is the best possible SNR for an N-bit ADC
Vinpp = Vref (0dB) ® SNR =6.02 N +1.76dB
Vinpp Þ -20dB ® SNR = (6.02 N +1.76 )dB-20dB
5.Performance specifications
(1)Missing codes (equivalent to monotonicity in DAC) Maximum DNL < 0.5 LSB or maximum INL < 0.5 LSB
ÞThe ADC is guaranted not to have any missing code.
(2)Conversion time
The time taken for the ADC to complete a single measurement including acquisition time of the input signal.
(3) Sampling rate
The speed at which samples can be continuously converted. Typically, the sampling rate is equal to the inverse of the conversion time except in the case of pipelining structure or multiplexing structure.
(4) Sampling-time uncertainty or aperture jitter
Due to the effective sampling time changing from one sampling instance to the next.
Sinusoidal waveform case:
Vin = Vref
2
13-4
CHUNG-YU WU
d |
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in |
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zero-crossing point |
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If V <1 VLSB for some sampling-time uncertainty t ,
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examples: 8-bit ADC, 250 MHz |
fin ÞDt <5 ps |
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16-bit ADC, 1 MHz |
fin ÞDt <5 ps |
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(5) Dynamic range
Dynamic range ≡
rms value of the maximum input (output) sinusoidal signal
rms value of the output noise plus the distortion when the same sinusoidal is present at the output
It is also called the signal-to-noise-and-distortion ratio (SNDR).
*Can be expressed as effective number of bits using the SNR formula on p. 13-3.
*Input frequency dependent.
6.Types of ADCs
Low-to-medium speed: |
(1) Dual-slope or Integrating ADC |
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Oversampling ADC |
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(3) |
Successive approximation ADC |
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(4) |
Algorithmic ADC |
High speed: |
(1) Flash ADC |
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(2) |
Two-step ADC |
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(3) |
Pipelined ADC |
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(4) |
Interpolating ADC |
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(5) |
Folding ADC |
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(6) |
Time-interleaved ADC |