material1 / different / Chung-Yu Wu - Analog Circuit Design

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Summary

2. Definition of SFDR (Spurious-Free Dynamic Range)

SFDR: The signal-to-noise ratio when the power of the third-order intermodulation products equals the noise power.

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§11-7 Summary

[16][15]

[4]

[1]

1.Kuang K. Chi et al, "A CMOS triple 100-Mbit/s video D/A converter with shift register and color map," IEEE J. Solid-State Circuits, Dec. 1986, pp. 989-995.

2.T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, "An 80MHz 8-bit CMOS D/A converter," IEEE J. solid-State Circuits, pp. 983-988, Dec. 1986.

3.L. Lteham, B.K. Ahuja, K.N. Quader, R.J. Mayer, R.E. Larsen and G.R. Canepa, " A high-performance CMOS 70-MHz palette/DAC," IEEE J. Soulid-State Circuits, pp. 1041-1047, Dec. 1987.

4.A. Cremonesi, F. Maloberti, and G. Polito, " A 100-MHz CMOS DAC for videographic systems, " IEEE J. Solid-State Circuits, June 1989, pp. 635-639.

5.N. Kumazawa, N. Fukushima, N. Ono, and N. Sakamoto, "An 8 bit 150 MHz CMOS D/A converter with 2 Vp-p wide range output," 1990 Symposium on

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VLSI Circuits, pp. 55-56.

6.Marcel Pelgrom, " A 50MHz 10-bit CMOS digital-to-analog converter with 75Ù buffer," Proc. of IEEE International Solid-State Circuits Conference, pp. 200-201, 1990.

7.C. A. A. Bastiaansen, D. W. J Greoeneveld, H. J. Schouwenaars, and H. A. H Termeer, " A 10-b 40-MHz 0.8-ìm CMOS current-output D/A converter," IEEE J. Solid-State Circuits, pp. 917-921, July 1991.

8.J.M. Fourier and P. Senn, " A 130-MHz 8-b CMOS Video DAC for HDTV Applications, " IEEE J. Solid-State Circuits, vol. 26, no. 7, pp. 1073-1077, July 1991.

9.Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, " A 10-b 70-MS/s CMOS D/A converter, " IEEE J. Solid-State Circuits, Apr. 1991, pp. 637-642.

10.H. Takakura, M. Yokoyam, and A. Yamaquchi, " A 10 bit 80MHz glitchless CMOS D/A converter, " 1991 IEEE Custom Integrated Circuits Conference, pp. 26.5.1-26.5.4.

11.D. Reynolds, " A 320 MHz CMOS triple 8-bit DAC with on-chip pll and hardware cursor, " IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1545-1551 DEC. 1994.

12.Shu-Yuan Chin and Chung-Yu Wu, " A 10-b 125-MHz CMOS Digital-to-Analog Converter (DAC) with Threshold-Voltage Compensated Current Sources, " IEEE Journal of Solid Circuits, vol.29, no. 11, pp. 1374-1380, Nov. 1994.

13.Chi-Hung Lin and Klass Bult, "A 10-b, 500-Msample/s CMOS DAC in 0.6 mm2," IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998.

14.Jose Bastos, Augusto M. Marques, Michel S. J. Steyaert, Willy Sansen, "A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC," IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.

15.Greet A. M. Van der Olas, Jan Vandenbussche, Willy Sansen, Michel S. J. Steyaert, and Georges G. E. Gielen, "A 14-bit Intrinsic Accuracy Q2 Random Walk CMOS DAC," IEEE Journal of Solid-State Circuits, vol. 34, no. 12, pp.1708-1718, Dec. 1999.

16.Alex R. Bugeja, Member, IEEE, Bang-Sup Song, Fellow, IEEE, Patrick L. Rakers, Member, IEEE, and Steven F. Gilling, Member, IEEE "A 14-b, 100-MS/s CMOS DAC Designed for Spectral Performance," IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 12, DECEMBER 1999.

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CH 12 CMOS Analog Comparators

§12-1 General Considerations

Purpose of Comparators: To compare two input voltages and produce a very large output voltage with an appropriate sign to indicate which of the two is large.

Types of MOS Comparators:

A. Differential-input OP AMP

_

+

The latch provides a large and fast output signal, whose amplitude and waveform are independent of those of the input signal. Well suited for the logic circuits usually following the latch.

If no latch: -1mV → +1mV input = -5V→+5V output

Gain 5000, 74 dB

If use latch: The output voltage of A must be larger than the combined offset and threshold voltage of the latch, which is about 0.2V

Gain = 200

(1)Static configurations

(2)Dynamic configurations B. Cascaded inverter stages

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§12-2 Differential-Input OP AMP Comparators

§12-2.1 Static Configurations without Latches

1.

+VDD

-VSS

*High Speed Comparator

*Open loop gain: ~80dB

*Output Swing: ±5V

*Propagation Delay (±10mV Vin ): ~1.2μs~2.4μs (15PF Load)

*Generally, compensation circuit is not needed since there is no feedback connection.

*Power Dissipation: ~10 mW

2.General-purpose comparators

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3. Comparator with level shift.

*Open loop gain: 60-80dB

*Output Swing: +5V→0V

*Propagation delay (±10mV, 15 PF): 1.0μs~0.8μs

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+VDD

φ2

Vbias

Vref

-Vss

S3

φ1a

* Practically, φ1a must go low first in advance of φ1 to avoid the clock feedthrough effect of S1 by φ1.

(2) Dynamic fully differential comparator

* S1 and S2 generate feedthrough voltages at A and Bcommon-mode voltage

* CMRR can be promoted by using negative common-mode feedback circuit.