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Chung-Yu Wu - Analog Circuit Design

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<<< < Предыдущая 10 11 12 13 14 15 16 17 18 19 20 2122 / 4922 23 24 25 26 27 28 29 30 31 32 33 34 > Следующая >>>

10 - 2

Vout

= VGO + mVtherm (γ -α)(1 + ln

)

-T

VGO

CHUNG-YU WU

= 1.16 -

7.02 ´10 −4 ×T 2

+ 1108

14.04 ´10−4T (T

+ 1108) - 7.02 ´10

−4 ×T 2

VGO

= -

T =TO

(T +1108) 2

14.04 ´10−4

−4 ×T

×T

7.02 ´10

= -

+ 1108

+1108)2

7.02 ´10−4 ×T 2

ÞV

= mV

therm

(γ -α)(1+ ln

)

+1.16

out

T +1108

14.04 ´10−4 ×T T

7.02 ´10−4

×T 2

×T

+1108

(T +1108)2

γ = 3.2, m = 1,α = 1,T

= 25O C

21.06 ´10

−4 (298)2

7.02 ´10 −4 (298)2

Þ V

out

(T )

= 1.16 + 2.2(0.0259) -

T =25 C

298 +1108

(298 +1108)2

= 1.093V

§10-2 Bipolar Bandgap Reference

+Vcc

Widlar bandgap reference

*Feedback element

is used to force

on.

*Q4

also serves as a start-up circuit.

*Vout

= I 2 R2

+VBE 3

I2 = I3

if I B2 = I B3

VBE1 -VBE 2

éln(

I S 2

R2>>R1

) + ln(

)

therm ê

I S 1

Vout

VBE3

VBE2

ïR

S 2

BE1

Vout

= VBE 3

+ í

mêlnç

+ lnç

÷úý×Vtherm

ï R

ë è

S 1

øû

I1 / I 2 = R2 / R1 If VBE1 = VBE 3

Adjust

R2 / R3

R2 / R1

and

I S 2 / IS 1

to give a suitable K

And Keep

I @ I2

to obtain

I B2 @ I B3

and

I S 3

to obtain VBE1 = VBE3 .

I S1

					10 - 3
				CHUNG-YU WU
	R2>> R1	V2
R1	R2>> R1	R2		4
		1		4
		VBE(on)
V1		+		3
Q1		Q2		3
Q1		Q2		ON State
		V2	2
		Cut-in State	2
	R3	-
		-			V1
		The operating point		4 is the	V1
		The operating point		4 is the
		desired operating point
		=>Need a start-up circuit.

§10-3 CMOS Real Bandgap Reference (BGR)

§10-3.1 CMOS BGR via BJTs and Resistors

Version 1:		Version 2:
N-well CMOS, positive VREF	N-well CMOS, Negative VREF

	I2
R1	I1
R1	R2
	-Vos+
	+
	CMOS
	OP AMP
	_	+
		+

VREF

- Q1

I1	I2	-
R1	R2
	-Vos +	+
		+
		CMOS
		OP AMP
		_
		VREF
	R3
		+
Q1	Q2
	Q2

-Vss -Vss

Q1,Q2:Substrage-well-source/drain parasitic vertical BJTs

= mV

I E

therm

I S

REF

= ±{V

(ln

+ ln

I s2

) + V

[

R3 + R2

]}

BE1

therm

I s1

10 - 4

Typical design values:

CHUNG-YU WU

I1=80μA

I2=8μA

R2 ≈

0.6V

= 75KΩ, R =

= 7.5KΩ, R =

60mV

= 7.5KΩ

8μA

Large resistanceèuse well resistors

R1,R2,R3:

n+/p+ diffusion resistors

n+ - poly resistors

well resistors

Both transistors are in the active region

VBE

Error analysis:

rb/A

â1

â2

1. Error due to base resistances

= V

+ V

rb I1

BE1

therm

I S

therm

1 +

Aβ1

β1

-Vss

I 2

= V

ln A + V

+ V

β1

+ r (

−

)

therm

1 +

β2

Aβ1

β2

If â1, â2 are not large enough or rb is too large,

è VBE due to rb and βis large.

1 +

R3 + R2

I s 2

= ±{V

+ V

(

) +

(ln

+ ln

β1

) +

r (

−

)}

REF

therm

I s1

1 +

b β2

Aβ1

β2

2.Error due to input offset voltage Vos

Vos=10mV, V

(1 +

) ≈ 10V

= 100mV

TC error due to

(1 +

10 ×10mV

= 264 ppm /o C

REF

1.26V × 300o K

REF

REF 0

3.Error due to Bias current variation

= V

Vtherm ln A

(R3=R1)

BE1

therm

I S1

Threm

R I S1

= Vtherm ln

Vtherm ln A

+Vtherm ln

(TO )

= I2

R1 (TO )I S1

R1 (T )

R1 is indep. of T

Þ VBE = Vtherm ln

Vtherm ln A

R1 (TO )I S1

R1 depends on T

Þ VBE = Vtherm ln

Vtherm ln A

+ Vtherm ln

R1(TO )

R1 (TO )I S1

R1 (T )

10 - 5

CHUNG-YU WU

1 dR

= V

-V

÷(T - T )- V

÷(T

-T )2

ideal

therm

R dT

therm

2R dT 2

TO ø

PTAT 2

PTAT

PTAT 3

PTAT

÷(T -T )

- ......

2R 2

therm ç

PTAT 3

PTAT

If R is only linearly dependent on T, we still have

PTAT 2

term

The

PTAT 2

term can be cancelled via curvature compensations.

4.TC Error due to Base Resistance

DVBE = rb

I 2

r I

æ 1 dr

dβ ö

TC error = (1 +

)

R V β

ç r dT I

dT β dT

ref

è b

Example : r

= 2KW , TC of

r = 1000 ppm / O C ,

= 30μA , β = 150 ,

TC of β = 7000 ppm / O C

ÞTC = –8.6 ppm / O C

5.Error due to base current

Base current cancellation technique

*To compensate for the different between the collector, emitter, or base current

10 - 6

CHUNG-YU WU

Version 1:	+VDD	Version2:
	+VDD	+VDD
		+VDD
I1	IB	IE
I1	IB
	IB	I1
		I1
IB
		IB
		IB
	IB
-VSS		-VSS

Ref:1.IEEE J .Solid-State Circuits, vol.SC-18, pp634-640, DEC. 1983 2. IEEE J .Solid-State Circuits, vol.SC-19, pp1014-1021, DEC. 1984

The circuit to obtain VREF from a BGR

+VDD

R1 R2

§10-3.2 Improved structure

VBIAS	ãN
	M1
	M1	M2

VBGR

+ VREF=VBGR(1+R4/R5)

R5 R4

Vo=VR1+VR2+VBE3				*Better matching
VR1= VBE1-VBE2=		KT		ln(αγ)

			q
Vo=VBE3+	KT	[ln(αγ)] (1+R/R) =>Bandgap Reference

10 - 7

CHUNG-YU WU

VBIAS

			M1

M4	M3	M2
M4	M3	M2

M110

10 - 8

4.	CHUNG-YU WU

M110

+VDD

M105 M104	M112
M111

M103
M103	M109		M108
	M109


		M110
		M110


M101	M	102	M	106		M107

-Vss

10 - 9

CHUNG-YU WU

5.Low Power Supply Circuit:

M101

M102

-Vss

*Low driving capability

Power supply limits:

	Low Possible	Voltage T=25°C

Bandgap reference	PMOS Inputs	NMOS Inputs
Topology

	VTP ≤ 1.0V	VTN ≤ 1.0V
1	1.5v	2.2v

2	1.95v	2.95v

3	1.90v	-

5	2.5v	1.5v

§10-3.3 CMOS BGR via lateral Transistor

Ref:IEEE J .Solid-State Circuits, vol. SC-20, pp.1151-1157, DEC. 1985

Structure of a lateral BJT in CMOS:

10 - 10

A.	CHUNG-YU WU

sub

metal

sub

Symbol:

Voltage reference via LBJT:

Conceptual circuit

		A:Current comparator
	Q2	VCC:Voltage-controlled current source
Q1		G:A negative voltage is applied to cause
Q1		G:A negative voltage is applied to cause
		accumulation.

Advantages:(1)The offset of the amplifier A has a negligible effect on VREF

(2)Simple structure.

Purpose of VCC : To provide a current path for IR1>>IB1,IB2

+VDD

1:A

Vref

-Vss

*High supply voltage.

*Two source follwers+one emitter follower in(A) current amp.=>higher current gain

10 - 11

CHUNG-YU WU

+VDD

Vref

-Vss

*Low supply voltage

*Low current gain in A

*R2 is trimmable

R4,R3,T3:VCC

R3: To keep T3 from quasi-saturation

R4:To sense the output voltage and transform it into the collector current of T3.

*All resistor are polyresistors

*Low output impedance.

Measured results:
VREF mean :1.2285V ;	standard deviation :150ìV
Minimal supply voltage	2.2V
Supply current	79ìA
Noise spectra	316nV	(white)	;	560nV	Hz (	1	,1KHz )
Noise spectra	Hz	(white)	;		Hz (	f	,1KHz )
PSRR(100Hz)	60dB
Load regulation (ÄVout/Iout)	3.6ìV/ìA
Chip area	0.42 mm2

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