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Pipelined ADCs
§13-7.1 A Pipelined 5-Msps 9-bit ADC
Ref.: IEEE JSSC, vol. 22, no. 6, pp. 954-961, Dec. 1987.
1. General pipelined ADC
2. Two-stage pipelined ADC
3. Prototype
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Ÿ OP AMP:
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Ÿ Comparators:
4. Measurement results:
2 SHA 
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§13-7.3 A Single-Ended 12-bit 20 MS/s Self-Calibrating Pipeline ADC
Ref.: IEEE JSSC vol. 33, pp. 1898-1903, Dec. 1998.
Advantages: concurrent processing of analog signals
Þoptimal speed and power dissipation
Þhigh speed and low power
Disadvantage: * Inherent passive component matching problem
Þhard to control and yield ¯
Þself-calibration and correction technique
*Latency Þ acceptable in most applications
1.The pipeline architecture
*CMOS SC implementation
Þconversion stage speed
µfeedback factor
µ(interstage gain)-1
Þ1-bit/stage for power and speed optimization.
Þsimple calibration.
*Transfer characteristic:
The output residue voltage Vout
Vout = 2Vin + D Vref
D = +1 for 0 < Vin < Vref
=-1 for -Vref < Vin < 0
*Digital correction technigue: Very attractive for submicron CMOS (small chip area)
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* The "radix = 2" overrange stage
To correct residues up to 1 Vref 2
outside the nominal ±Vref range for
Vin.
Transfer characteristic:
Vout = 2Vin + 2 × D Vref
D = +1 |
1 Vref < Vin < Vref |
|
2 |
=0 - 12 Vref < Vin < 12 Vref
=-1 -Vref < Vin < - 12 Vref
Lower feedback gain for the overrange stage
Þmaximum operating frequency ¯
*Overall architecture only 3 overrange stages are used for digital correction.
2.Self-calibration and correction algorithm
*Starting from the eleventh pipeline stage and working toward the MSB stage. The rest of the stages (12-15) are not calibrated.
*For each calibration stage, the calibration consists of
(1)forcing an analog input value of 0V (differential)
(2)forcing the digital decision to the left and to the right of the transition.
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* The calibration coefficient
Memi = code_l - code_h
Vout = Vref |
Code_l=0 |
Vout = -Vref |
Code_h=0 |
Þ Memi = 2 DVout @ DVin
one coefficient for regular stage.
two coefficients for overrange stage.
All the correction coefficients are stored in 15 registers.
*All the digital correction is
performed in 16 bits, and the last 4 LSB's are truncated for the final 12-bit output code.
*Global offset and full-scale error can be calibrated.
3.Implementation of Analog Blocks.
*The single-ended to differential input S/H:
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* Input common-mode fb amp.
*op amp
(telescopic op amp)