Добавил:

Upload Опубликованный материал нарушает ваши авторские права? Сообщите нам.

Вуз:

Национальный исследовательский университет «МИЭТ»

Предмет:

[НЕСОРТИРОВАННОЕ]

Файл:

Chung-Yu Wu - Analog Circuit Design

.pdf

Скачиваний:

Добавлен:

05.06.2015

Размер:

29 Мб

Скачать

☆

<<< < Предыдущая 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 4546 / 4946 47 48 49 > Следующая >>>

15-18 CHUNG-YU WU

Vo (s)

(

2 +(

)S +

G1G3

H(S)=

CACB

V (s)

G3G4

+(GB )S

+ CACB

3. Four-transistor integrators

Vdiff ≡Vpo-Vno

(Vpi

−Vni ) +

(Vni −Vpi )

srDS1c1

srDS 2c1

where rDS1=

(

)

−V

−V )

L 1

rDS2=

(

)

−V

−V )

All four transistors are matched

=>Vdiff= sr1 c (Vpi −Vni )

DS 1

where rDS=				1
where rDS=	u	c		(	W	)(V		−V		)
					W

	n		ox		L		c1		c2

16-1 CHUNG-YU WU

CH 16. Oversampling Data Converters

§16-1 Fundamental Concept

§16-1.1 Oversampling without noise shaping

1. Quantization noise modeling			e(n)
1. Quantization noise modeling
x(n)	y(n)	x(n)	+	y(n)
	Quantizer		+
	Quantizer
		e(n) ≡ y(n) − x(n)

* e(n) can be approximated as an independent random variable uniformly

distributed between ± ∆ where	∆ is the difference between two adjacent
2
quantization levels, i.e. VLSB.	∆2
* The quantization noise power =	∆2	= P
	12	e
	12

* The quantization noise power is independent of the sampling frequency fs.

* The spectral density of e(n), Se(f) is white and all its power is within ±

Se(f)

2fs Kx 2 df

= Kx 2 fs

∆

2fs Se2 ( f )df

∫−

Height Kx

=>Kx=(

∆

)

2. Oversampling Advantage	− fs	0	fs
2. Oversampling Advantage	2		2

H ( f )

		1		x(n)	quantizer	y(n)	y2 (n)
					quantizer	y(n)	H(f)
				fo	N-bit		H(f)
					N-bit

							filter
− fs	-f	f	fs	f	fs
− fs	-f	f	fs	f
2	o	o	2

Oversampling ratio OSR ≡ 2ffo

16-2 CHUNG-YU WU

Assume that the input signal is a sinusoidal wave between 0 and ∆2N. The signal power Ps is

Ps=(		N	2		2 N
Ps=(	∆2	2	)2 = ∆	2
	2	2		8

With H(f), Ps remains the same since the signal's frequency content is below fo, but the quantization noise power Pe becomes

Pe= ∫−2fs

Se2 ( f ) H ( f ) df = ∫−fofo Kx 2 df = 2 fo

∆

( 1 )

OSR

OSR ↑×2 => Pe ↓

or -3dB, or 0.5 bits

SNRmax=10log(

) =10log(3

22 N ) +10log(OSR)

=6.02N+1.76+10log(OSR)

=>SNR enhancement obtained from oversampling: 10log(OSR). SNR improvement of 3 dB/octave or 0.5 bits/octave

3.The advantage of 1-bit D/A converter

*Oversampling improves the SNR, but it does not improve linearity.

*Theoretically, 1-bit converter with fo=25 KHz can obtain a 96-dB SNR(16 bits) if the sampling frequency fs=54,000 GHz!

*The advantage of a 1-bit DAC is that it is inherently linear.

Vout	always linear

Bin

§16-1.2 Oversampling with noise shaping

1. The system architecture of a ∆Σ oversampling ADC is shown in the next page

16-3 CHUNG-YU WU

Oversampling Delta-Sigma Analog-to-Digital Converters:

Analog Signal

Minimum

Anti-Aliasing

Filter

fs >> 2fo

Delta-Sigma

A-to-D Converter

(Modulator)

Analog

Delta-Sigma

Modulator

1-bit stream

fs >> 2fo

2. Noise-shaped ∆Σ modulator

u(n)		X(n)	1-bit	y(n)
u(n)				y(n)
+	H(Z)
+	H(Z)		Quantizer
	-		Quantizer
	-
		DAC
		1-bit

Decimation Filter

DSP


DSP	.	Multi-Bit
Decimation	.	Multi-Bit
Decimation	.	Output
Chip
Chip

2 fo =	1	Nyquist
	(OSR)T Rate PCM
Digital	OSR
Low-Pass	OSR
Filter
Down Sampler
		e(n)
u(n)	H(Z)	X(n)	y(n)
+	H(Z)	+
-
		DAC
		1-bit

Two independent inputs: U(z) and E(z)

Signal Noise

Signal transfer function STF(z) ≡

Y (z)

H (z)

U (z)

1+ H (z)

Noise transfer function NTF(z) ≡

Y (z)

E(z)

1+ H (z)

=>Y(z)=STF(z)U(z)+NTF(z)E(z)

H (z)

→ ∞ for 0<f<fo =>

STF (z)

→1

and

NTF (z)

→0

=> Quantization noise ↓ and signal unchanged. 3.First-order noise shaping:

16-4 CHUNG-YU WU

H(z)=

z−1

(Noniverting Forward-Euler SC integrator)

1− z −1

=>STF(z)=

H (z)

= z −1

1+ H (z)

NTF(z)=

−1

jωT j2πf/fs

(1− z

)

z=e

1+ H (z)

-j2πf/fs

πf

×(2 j) ×(e

− jπ f

/ fs

NTF(f)=1-e

=sin( fs

)

NTF ( f )

= 2sin(πf )

The quantization power noise power over 0 to fo is

Pe=

Se2 ( f )

NTF ( f )

2 df

(

∆2 )

[2sin(π f

)]2 df

∫− fo

Since fo << fs, i.e. OSR>>1, sin(

πf

)

π f

=> Pe (∆2

)(π 2 )(

2 f )3 = ∆2π 2

(

OSR

Ps=

∆2

2 N

(OSR)

=> SNRmax=10 log(

) =10log(

) +10log[

]

π 2

=> SNRmax=6.02N+1.76-5.17+30 log(OSR) Double OSR => SNRmax ↑ by 9dB or 1.5bits/octave

Without noise shaping: SNRmax ↑ by 3dB/ octave or 0.5bits/ octave.

Y=Z-1U+E(1-Z-1)	E
Block diagram:

U +

H (z) =	z−1	+
	1− z−1		Y =UZ −1 + E(1−Z −1 )

								16-5
	SC implementation:							CHUNG-YU WU
	SC implementation:
			C			2
		C			Comparator		Latch
	2	1	+	1		+	Latch	Y
	2	1	_	1		_	(2)	Y
U			_			_		1

	1	2				phase 2
	1	2				phase 2
	A′		H(Z)			Reset		. 5
	A′		H(Z)		Quantizer(1-bit ADC )			. 5
					Quantizer(1-bit ADC )
								0
	C			1-bit DAC				-. 5
		1						-. 5
		1
				A	0. 5
		2				Control signal		-1
Can be eliminated by connecting					-0 . 5	Control signal
Can be eliminated by connecting					-0 . 5
the node A Directly to the node A'.

First-order noise shaping with 2-bit ADC and 2-bit DAC

U		z−1		2-bit	Y
+		1 − z	−1	A / D
	-	1 − z	−1


				2-bit
				D / A
		0. 5	+
		0. 5
				Y	1
			+	Y
		0	+
		0

					. 5
		-0. 5	+		0
		-0. 5			0
.75	.25 -.25 -.75
					-. 5
		MUX			-1
		MUX

Control line

16-6 CHUNG-YU WU

4. Second-order noise shaping

U +

z−1

Quantizer

1− z−1

DAC

STF(Z)=Z-1

NTF(Z)=(1-Z-1)2

Y=Z-1U+(1-Z-1)2E

NTF ( f )

=[2sin(

π f

)]2

=> Pe ∆2π4 (

OSR

SNRmax=10log(

) =10log(

3 2N ) +10log(

) +10log(OSR)5

π 4

=6.02N+1.76-12.9+50log(OSR)

OSR×2 => SNRmax↑ by 15dB/Octave or 2.5 bits/Octave

General formula of SNRmax with k-order noise shaping:

SNRmax=6.02N+1.7610log(

2k +1

) + (2k

+1) 10log(OSR)

π4

OSR×2=> SNRmax↑by 3(2k+1)dB/Octave or 0.5(2k+1)bits/Octave

Noise-shaping transfer functions:

	NTF ( f )	Second-order
		First-order
		No noise shaping
			f
0	f 0	f s	f s
		2

The SC implementation of the second-order ∆Σ modulator is shown in the next page.

*Single-ended structure

*Can be converted into fully differential structure for better noise rejection and

16-7 CHUNG-YU WU

linearity.

* The capacitor and switches in the feedback path to OP2 can be reduced as shown on page 16-5.

SC implementation: Single-Ended type circuit diagram

						C			V+
								2
							1			Control
							1			signal
									V-	signal
						C			V-
								2	1-bit
								2	DAC
							1		DAC
							1
		C	C		C	C			COMP-1
U		C	C

	2	2		2		1			2
			-OP1			-OP2		-	Latch	Y
			-OP1			-OP2	1	-	Latch
	1	1	+	1	2	+	1	+	(2)
	1	1	+	1	2	+		+	(2)
								Preamplifier
							Comparator as quantizer or 1-bit ADC

16-8 CHUNG-YU WU

§16-2 System Architecture of Oversampling ∆Σ ADC

1. Architecture

xsh (t)

xin (t)

(t)

Anti-

Sample-

∆∑

aliasing

Mod

and-hold

f s

filter

xdsm (n)		xlp (n)		xs (n)
	Digital
	Digital
	low-pass			OSR
f s	low-pass		f s	OSR
f s	filter		f s		2 f 0
					2 f 0

Decimation filter

2. Signals and spectra	Analog	Digital
X c (t)		xc ( f )
X sh (t)
	t	f 0			f s	f
xdsm (n) = ±1.000000K		xsh ( f )
xdsm (n) = ±1.000000K						f
		f 0			f s	f
3		f 0			f s
3	n
12 4...	n	xdsm (ω)
12 4...

x lp ( n )		2π(f	/f )	π	2π	ωTs
x lp ( n )		π/60	s		2π
	n	xlp (ω)
123.....	n
123.....						ωTs
		π/6		π	2π	ωTs
		2π(f	/f ) =	π	2π
xs (n)		0	s	OSR	OSR=6
				OSR	OSR=6
		xs (ω) 16-bit resolution in 16-bit ADC
3...	n					ω
12		π 2π 4π 6π			8π 10π 12π	T0
		π			2π ωT s
		6			2π ωT s
		6

* The decimation process does not result in any loss of information, since the bandwidth of the original signal was assumed to be fo. The spectral information is

spread over 0~	π	in Xep and 0~π in Xs.
	6

16-9 CHUNG-YU WU

§16-3 System Architecture of Oversampling ∆Σ DAC

1. Architecture

xdsm (n)

xs (n)

xs2 (n)

xlp (n)

xda (t)

xc (t)

Interpolation

∆∑

1-bit

Analog

OSR

(low-paaa)

Mod

D / A

low-pass

2 f 0

f s

filter

f s

		Digital Analog
OSR ≡ 2 f	()	Digital Analog
OSR ≡ 2 f	()
2. Signals and spectra

xs (n) xs2 (n)

(2)	(3)	n
123...(1)		n
123...(1)

x lp ( n )

123.....	n

xdsm (n)

xda (t)

n,t

xs (ω)

π 2π 4π 6π 8π 10π 12π ωT0

xs2 (ω)

(2π f 0)	f s	ωTs
		2π
xlp (ω)		ωTs
(2πf 0 )	f s
		2π

	xdsm (ω)	ωTs
	(2πf 0 ) f s	ωTs
	(2πf 0 ) f s	2π

X c (t)	xda ( f )
	f 0		f s	f

t	xc ( f )
Time	f 0		f s	f
		Frequency

<<< < Предыдущая 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 4546 / 4946 47 48 49 > Следующая >>>

Соседние файлы в папке different

#
05.06.2015209 Кб405-1.doc
#
05.06.2015108 Кб405.doc
#
05.06.20159 Мб40Advanced Mathematical Methods for Scientists and Engineers.pdf
#
05.06.20152 Мб44Allen&Holberg - 10+11.pdf
#
05.06.20152 Мб60Allen&Holberg - Analog CMOS Circuit Design.pdf
#
05.06.201529 Мб61Chung-Yu Wu - Analog Circuit Design.pdf
#
05.06.20152 Мб45Structure and Interpretation of Signals and Systems (E. (1).djvu
#
05.06.20152 Мб39Structure and Interpretation of Signals and Systems (E.A.Le.djvu
#
05.06.20154 Мб47System on a Chip Verfication_Methodology and Techniques.pdf
#
05.06.20151 Мб60АИС-1 (до ОУ).doc
#
05.06.2015798 Кб70АИС-2 (ОУ).doc