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Национальный исследовательский университет «МИЭТ»

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Chung-Yu Wu - Analog Circuit Design

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14-40 CHUNG-YU WU

SCF:

14-41 CHUNG-YU WU

General Procedures for the approximate design of SC ladder filter

:1. A doubly terminated LC two-port is designed from

the SCF specifications can be prewarped using the relation:

Wa =

sin(

ωT

)

which represents the frequency transformation due to

the LDI transformation implicit in the design

produce.

Inverting SC integrator + Noninverting SC integrator

H(z)=

/ C

)

(C / C

)

noninv

z−1

inv

1 − z−1

1− z−1

− Kz −1

− K

(1 − z

−1

)

− z−

Ton z=ejωT

jωT

+ K

> H(e

4sin2 (ωT / 2)

LDI mapping (Lossless discrete integrator):

Sa=

(z − z−1 )

− z−

is used

> Sa=

)

Sin(ωT )

> ωa=

T / 2

2.The state equations of the LCR circuit are found. The signs of the voltage and current variables must be chosen

such that inverting and noninverting integrators alternate in the implementation. If inductor loops exit, the inductive node currents can be used.

14-42 CHUNG-YU WU

4.The block diagram or signal flow graph (SFG) is constructed from the state equations. It is then transformed (directly or via the active-RC circuit) into the SCF.

5.If necessary, additional circuit transformations can be performed to improve the response of SCF.

§14-10 Exact Design of SC Ladder Filters

* Ladder synthesis based on the bilinear Sa-to-z transformation

Sa=	2	z −1	(1)jωa─axis >unit circle

	T	z +1
	T	z +1
			(2)preserves the flatness of PB and SB

§14-10.1 Third-order SCF (Low-pass with finite transmission zero)

C2'=C2+CL2

-CL2= −T 2

4L2

-V1

−

(C1

)

+C2

-I

−

L 2

sa L2

V1 +Vin	+ saC2′V3	− I
			2 ,

Rs
−V3 ],

V3=	−1		′			V3
		− sa C2	V1	− I2	+		.
	sa (C2′+C3)
						RL

LCR Prototype Circuit:

14-43 CHUNG-YU WU

Flow diagram

The center block has the transfer function:

H(Sa)=SaCL2-	1	=	1− Sa	2 L2CL2	= −	1−(SaT / 2)2
	Sa L2		Sa L2			Sa L2

Transformation of the blocks into SC circuits:

(1)Finding Q-V relations of all blocks and branches in the Sa domain.

(2)Transforming the Q-V relations into the z-domain.

(3)Realizing the transformed z-domain equations into SC circuits.

Five different blocks:

(a) The input branch 1Rs

14-44 CHUNG-YU WU

Q	(S	)=	1	V	1
			Rs
in	a			in Sa

Qin (z)= T z +1Vin (z)

2 z −1 Rs

> (1-z-1)Qin = 2TRs (1+z-1)Vin(z)

qin(tn)-qin(tn-1)= 2s [Vin(tn)+Vin(tn-1)]

SC realizations:

Optional. To guarantee the charge flow only when φ1=1

φ1

CS/2

[Vin (tn ) −Vin (tn −1 )]

Vin

Virtual

Cs : Cs Vin (tn-1)

ground

* Not stray insensitive.

Cp + Cs not Cs

(b) The feedback branch

Rs ,

Vin

Virtual

−

: −

[Vin (tn ) −Vin (tn−1 )]

φ2

ground

-C /2

φ2 CS

φ2

Cs: CsVin(tn)

φ1

[Vin(tn)+Vin(tn-1)]

* Stray insensitive.

(c)The branches SaC

Q =CS

Only a C is required.

a Sa

(d) The blocks -

SaC

= −C > OP with a feedback capacitor C.

has been merged into the feedback capacitors

(e) The center block

-I2=-

−(Sa T

(V1-V3)

Sa L2

Q(Sa)=

− I2

= −

1 −(Sa T 2)2

(V1-V3)

S 2 L

Q(z)

= −

1 −[(z −1) /(z +1)]2

= −

4CL 2 Z

V (z) −V (z)

(4L /T 2 )[(z −1) /(z +1)]2

(z −1)2

-1

4CL

−V )

∆Q(z)=(1-z

)Q(z)=

z −1

∆Q(z)

L 2

z−1

−

− 4C

/ C

=(−Cz

1 )(

)(C)

−V

1 − z−1

Realizations:

-V1

ψ2

ψ1

ψ2

Virtual

groundC2/4C

ψ1

ψ2

ψ1

ψ1 ψ2

Virtual Q ground

V3 ψ2

The final realization is shown in the next page.

*This circuit is not fully stray insensitive.

*The negative capacitor − C2s

CA and CB, respectively.
CA=C1+C2' −	Cs	CB=C2'+C3	−	Cs

2			2

* Why C2', -CL2 ?

To create a block which is realizable by SC circuit.

14-45 CHUNG-YU WU

ψ1

ψ2

ψ1

SCF:

ψ2

CS / 2

Vin	ψ	ψ2
		1

ψ1 ψ2

C'2

ψ1 ψ2

- +

14-46 CHUNG-YU WU

ψ2 ψ1

ψ1 ψ2

ψ2 ψ1

Vout

The complete bilinear ladder circuit equivalent to the LCR circuit

14-47 CHUNG-YU WU

§14-10.2 Bandpass LCR filters

LC prototype Circuit: V1

2	V2	V
		3
I2	IL2
	IL3	L
C2	L2	3
C2	L2

-V2 can be produced as:

+ -

-V2

I2=(SC1+	1	) (V1-V2)+(SC3+			1		) (V3-V2)-	V2
	SL				SL			SL	2

	1				3
Note that			1 −(Sa T	2)2		is realizable !
			Sa L

>I2(S)=S[(C1+CL1)V1+(C1+C3+CL1+CL3)(-V2)+(C3+CL3)V3]

+ ( 1 − T 2 s ) [Γ1V1+(Γ1+Γ2+Γ3)(-V2)+ Γ3V3]

S 4

Where CLi ≡ T 2 , Γi= 1 4Li Li

First Term:

Q2'(S)=(C1+CL1)V1+(C1+C3+CL1+CL3)(-V2)+(C3+CL3)V3 Can be realized by unswitched capacitors.

Second Term:

		T z +1		2			T 2	][Γ1V1+(Γ1+Γ2+Γ3)(-V2)+ Γ3V3]
Q2"(Z)=[(			)			−	4

		2 z −1
=		T 2 z−1			[Γ1V1+(Γ1+Γ2+Γ3)(-V2)+ Γ3V3]
	(1 − z−1 )2

14-48 CHUNG-YU WU

The same as before but now three functions are superposed together. ( ∆Q2 "/V1 , ∆Q2 "/(−V2 ), ∆Q2 "/V3 )

Conditions:

C4C7

= T 2

= 4CL1 ;

C5C7

=T 2 (

) = 4(CL1 +CL2 +CL3 )

C6C7 = T 2 = 4CL3

C8 L3

Stage providing Q2”(z):

V1	-V2	V3			LC prototype circuit:
					LC prototype circuit:
C	C	C6		C1		C3
4		5			V2	V
					V2	V	3
							3
				V1
				L1	C2	L3
					C2	L2
	C8
			Q "(z)
		C7	2	Vitrual
		C7		Vitrual
				ground

SC realization:

Design equations:

CL1=T2/(4Li)

c1=C1+CL1

c2=C1+C2+C3+CL1+CL2+CL3

c3=C3+CL3

CL1

Vt=-V2

c4= 4 c

c =

4 c8

)

c c6= 4 c8 CL3

c7, c8	arbitrary	c7	c8
		c7	c8
			Vb

LC prototype circuit with RS:

Vin

14-49 CHUNG-YU WU

SC realization:

Vin c1	c
	8

c	c3	c4
	2
		-V1
		c5
c	7	c6
	7

Design equations:

C		∆	T 2		, C	∆	T
			4L				R
	Li				s			s
				i
c1=		Cs		,	c2=c3=C9

		2

c4=C1+C2+CL1+CL2-CS/2

c5=4 cc6 (CL1 +CL2 )

c8=C2+CL2

c c9=4 c6 CL 2

c6, c7 arbitrary

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