material1 / different / Chung-Yu Wu - Analog Circuit Design

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§16-4 High-Order Modulators

Multi-stAge noise SHaping (MASH) architecture:

To use a cascade-type structure where the overall higher-order modulator is constructed using lower-order ones.

=> The stability could be maintained.

§16-5.1 Limitations on accuracy and linearity

A. Noise

Thermal noise in resistors, conducing switches, op-amps. Usually aliased by sampling

1/f op-amp noise, dc offset Supply, ground and substrate noise clock feedthrough noise

clock jitter noise quantization noise leakage

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B. Nonlinear effects

R&C nonlinearities Amplifier nonlinearities Finite op-amp slew rate

Signal-dependent clock feedthrough noise Signal-dependent sampling aperture noise Internal A/D and D/A nonlinearities

Linearity of 1-bit DAC:

1.The two output levels somehow become functions of the low-frequency signals=> Linearity limitation

Power supply voltage are changed for different low-frequency signals to cause distortion.

=> must be well-regulated.

The clock feedthrough of the input switches is also dependent on the gate voltage and thus the supply voltage.

=> low-frequency input signal dependent

The clock jitter could be a function of the low-frequency input signals.

2.The memory between output levels also causes severe linearity limitation.

Typical

Ideal

V2

δ1, δ2: The area difference of the present binary state with different past states.

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periodic pattern with 16 cycles and some power at dc and 16fs . => lowpass filter

=> dc level 83 and 16fs tone

( fo=16fs is assumed and lowpass filter will not attenuate fs/16 signal)

=> Low-frequency tones cannot be filtered out by the lowpass filter and can lead to annoying tones in the audible range. They exist even in high-order modulators. There tones might be a signal varying over some frequency range in a random-like fashion.

Dithering technique to reduce idle tones.

To add the dithering signal to the modulator just before its quantizer. The dithering signal has a white-noise type spectrum and is a random (psuedo-random) signal.

The dithering signal breaks up the tones so that they never occur. Add about 3-dB extra in-band noise

Require rechecking the modulator's stability.

§16-6 Advantages and Applications

Advantages of Delta-Sigma Converters:

Low-Complexity Analog, High-Complexity Digital High-Resolution Conversion

Low-Precision Analog (no trimming) Simple Anti-Aliasing Filters

No Sample & Hold Needed

Can be Built Completely In CMOS

Overall Small Chip Area in Fine-Line Technology Can be Integrated on Chip With Other DSP Functions Ideally Suit for Rates up to and Including Audio Band

Commercial Applications Well-Suited for Delta-Sigma ADC Standard Voice Band Telephony

13-bit dynamic range, 8-bit linearity (u/A-Law), 8KHz Sampling rate Digital Mobile Radio (same req. as above)

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High-Precision Voice-Band (CCITT V.32 9600-Baud Modems)

14-15 bit dynamic range, 12-bit linearity, 3-4kHz BW, 9600 Sampling rate ISDN Wideband Speech (CCITT G.722)

13-bit dynamic range, 16kHz Sampling rate ISDN U-Interface

13-bit dynamic range, 80kHz Sampling rate, 160kb/s Transmission Rate Audio-Band (CD, DAT; stereo (2))

16-18-bit (18-20 bit) resolution, 14-16 bit)(15-16bit) linearity, 48kHz Sampling Rate

5 1/2 Instrumentation A/D Converter

20 bit resolution, 0.1-10Hz BW with Self-Calibration Circuit Integration with Digital Signal Processors

Ideally Suited for Rates up to and Including Audio Band

A variety of applications from voice-band through audio-band

§16-7 Examples

2nd-order ∆Σ modulator implemented by fully differential SC circuit.

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CH 17 Phase-Locked Loops (PLLs)

§17-1 General architecture and Operational Principle

1.Applications of PLLs: 1. Clock recovery in communication and digital systems.

2.Frequency synthesizer used in televisions or wireless communication systems to select different channels.

3.Demodulation of FM signals.

If the phase detector is of analog-multiplier type, its output voltage Vpd can be written as

Vpd=KMVinVosc=KM Ein Eoscsin(ωt)cos(ωt-φd)

where φd is the phase difference between the input signal Vin and the output Vosc of the VCO.

Ein Eosc [sin(φd ) + sin(2ωt −φd )] 2

Since the lowpass filter is to remove the high-frequency (2ω) term, the signal Vcntl is given by

The frequency of VCO can be expressed as

ωosc=KoscVcntl+ωfr

where ωfr is the free-running frequency of the VCO with its control voltage Vcntl=0.

=> Vcntl= ωi n −ωf r

Kosc

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where ωin is the frequency of the input signal, which is equal to the frequency of VCO output when the PLL is in the locked state.

3.Linearized small-signal analysis

When a PLL is in lock, its dynamic response to input-signal phase and frequency changes can be well approximated by a linear model, as long as these changes are slow and small about their operating point.

A signal-flow graph for the linearized small-signal model of a PLL when in lock:

* H(s)=0 as s→0 => ∆φin=0 leads to ∆Vcntl=0

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The above second-order s-domain transfer functions have ωo and Q as

* Q= 12 → good settling behavior

Q= 13 = 0.577 → maximally flat group delay

Q= 12 = 0.707 → maximally flat amplitude response

In most cases, when ωo<<ωfr, we have

1

τZ>> K pll 2

The transient time constant τpll of the complete loop for small phase or frequency changes can be expressed as

τpll ω1 o

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Design considerations: 1.Choosing Kpd and Kosc based on practical considerations 2.Choose τp to achieve the desired loop settling time 3.Choose τZ to obtain the desired Q of the loop

4. Capture range and acquisition time

Capture range: The maximum difference between the input signals' frequency and the VCO free-running frequency where lock can eventually be attained.

The capture range is on the order of the pole frequency of the lowpass filter.

Acquisition time: The time required to attain lock If the initial difference between the input signal's frequency and the VCO frequency is moderately large, the acquisition time tacq is

tacq Q(ωi n −ωosc )2

ωo 3

* If a PLL is designed to have a narrow loop bandwidth ωo, tacq can be quite large and lock is attained too slowly.

Solution: 1. To add a frequency detector that detect when ωin-ωosc is large. Then drive the loop toward lock much more quickly. When ωin-ωosc is small, the frequency detector and the driver are disabled.

2.To design the lowpass filter with a programmable pole frequency ωo. Initial acquisition: ωo↑ speed up acquisition.

3.To sweep the VCO's frequency range during acquisition with the PLL disabled. When ωosc→ωin, sweeping is disabled and PLL is activated.

5.Lock range

Lock range: Once lock is attained, the PLL remains in lock over a range as long as the input signal's frequency ωin changes only slowly. This range is the lock range, which is much larger than the capture range.

Vcntl-max=Klp KM Ein Eosc =KlpKpd

2

=> ωlck = ± KoscKlpKpd