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Two-Step Flash ADCs or Subranging ADCs with:
(1)Two Resistor (R) Ladders
*Need 2(2N/2-1) comparators & R tapes.
*Need high-performance op amp.
Nonlinearity caused by the mismatch of the two resister ladder.
High-performance op amp is not easy to be achieved (especially for 3 V Vdd).
(2)Single Resistor Ladder
*Need 2N-1 R tapes.
*Need 2(2N/2-1) comparators.
As many R tapes as full flash type.
No op amp is required.
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CHUNG-YU WU
§13-6.1 Subranging (Two-Step Flash) ADCs
8-bit 50MHz CMOS Subranging ADC with Pipelined Wide-Band S/H
Ref.: IEEE JSSC, pp. 1485-1491, Dec. 1989.
Conventional subranging A/D converter:
Trade-offs in Subranging and Flash 8-bit ADC |
|
|
|
Flash |
Subranging |
Total comparators |
256 |
31 |
Clock cycles/conversion |
1 |
2 |
Relative speed |
1 |
0.5 |
Relative input loading |
1 |
0.12 |
Relative power dissipation |
1 |
0.2 |
Relative die size |
1 |
0.4 |
Typ. Differential Linearity Error |
0.4 LSB |
0.3 LSB |
Typ. Integral Linearity Error |
0.7 LSB |
0.5 LSB |
*High accuracy is required only for the S/H circuit and the D/A subconverter. (S/H is to reduce the effect of signal delay differences in the large-area chip.)
*Very difficult to develop a high-speed (video) and high-accuracy MOS S/H circuit.
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CHUNG-YU WU
*The conversion rate degrades. (Pipelined structure may be used)
*The linearity of the complete converter depends on the accuracy of the gain matching among the first A/D, the D/A, and the second A/D subconverters.
New structure: (4-bit conceptual structure)
Subranging A/D converter using combined DAC/subtraction technique: (a) block diagram and (b) subranging process
*Combined DAC/subtraction Technique
*No current flows through the switches Þ No degradation in linearity in DAC
*Amplifiors's settling time < 2 ns
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CHUNG-YU WU
Conventional MOS S/H:
SF:
*The switch opening time is influenced by input voltages Þ severe distortion.
*Poor linearity.
Integrator-type S/H:
*The same switch closing time.
*Close loop configuration enhances the linearity.
*Difficult to obtain a fast-settling speed that ensures 8-bit accuracy. Imposed by the relatively high output resistance of the amplifier and the clock feedthrough error of the MOS switch.
Conventional MOS S/H: (a) source follower type S/H,
(b) waveform of clock f and switch opening time deviation for source follower S/H, and (c) integratortype S/H
New S/H:
*Bandwidth-enhanced integrator-type S/H circuit.
*CMOS transmission gate with dummy transistor (clock feedthrough ¯)
*Compensation
CC |
= |
R F |
CH |
(1+ |
RSW |
+ |
RSW |
) pole-zero |
Bandwith-enhanced integrator-type S/H |
|
R1 |
|
|||||||
|
|
R I |
|
|
R F |
||||
cancellation. Þ Bandwidth-.
*CH=1 pF, Cc=1.2 pF, RF = RI = 1KW, RSW = 100W Þ 8-bit, 50 MHz. Tsettling = 12 ns ~ 8.5 ns for 2V step.
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CHUNG-YU WU
Block diagram of pipelined S/H and subtractor
*The output of the subtractor is set to analog ground by closing the switch for the limiter.
High-speed operational-amplifier circuit diagram
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Simulated linearity characteristics for S/H circuits
Comparator for the second A/D subconverter |
|
|
* Comparators for the second A/D subconverter have an inaccuracy £ |
1 |
LSB. |
|
4 |
|
(3 mV at 3V input) (FS)
* ³ 100 MHz with a 7-8 mW power dissipation.
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CHUNG-YU WU
Timing diagram for pipelined subranging A/D converter
Experimental results:
1 μm CMOS, 5V single power supply, sampling rate 50 MHz.
Effective bits and gain as a function of analog input frequency
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CHUNG-YU WU
§13-6.2 10-bit 5-MSPS CMOS Two-Step Flash ADC
Ref.: IEEE JSSC, vol. 24, no. 2, pp. 241-249, Apr. 1989.
1.Classical two-step flash ADC
*Limited by matching between the MSB ADC and DAC transitions
*Limited by op-amp settling time (conversion rate)
2.New structure
*No OP amps.
*No gain block
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3. Circuit implementation
*Shared binary weighted capacitor array for the MSB ADC and DAC and the LSB ADC.
Þ mismatches ¯