1
vs. f
H(ejωT)
3. SC realization
(1) H0(z)= z +1
z − 0.9063
CD
Vin |
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C |
-1 |
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(1+Z-1) |
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CS/2
fp
0 f fp
H0(z)=- |
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× |
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z −CE /(CD +CE ) |
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CD +CE |
Cs=2 arbitrarily chosen φ1=>CE=0.9063 , CD=0.0937
φ2
Vout
(2) H1(z)= |
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+C z +1 |
Q1= |
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12 |
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Low-Q |
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The SCF is shown on P.14-21.
The component values are: C1"=a0=1, C1'=a2-a0=0,
C2=C3= 
b1 +b2 +1 = 
(e1 +1) / f1 +1 0.12436,
14-61 CHUNG-YU WU
C1=(a0+a1+a2)/C3 0.30358,
C4=b2-1=1/f1-1 0.12939, CA=CB=1.
(3) H2(z)= |
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Q2= |
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12 |
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4.33 =>High-Q |
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The SCF is shown on P.14-23. |
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The component values are: |
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C1"= a2 / b2 |
= f2 0.96845 |
C1 '= (a1 −a0 ) / b2 c3 |
= 0, |
C2 = C3 = 
(1+b1 +b2 ) / b2 = 
f2 +e2 +1 0.13795,
C1=(a0+a1+a2)/b2C3=(2+c2)f2/C3 0.58645, C4=(1-1/b2)/C3=(1-f2)/C3 0.22873.
(4)Overall SCF
* Ho (low-pass linear section) is placed first
=>High-frequency out-of-band signals and input noise can be attenuated. The antialiasing filter preceding the SCF has a lower requirement.
* H2 (high-Q section) is placed to the center=>good signal-to-noise ratio
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CD |
φ1 |
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C2 |
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CS/2 |
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C4 |
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C |
S |
φ |
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CB |
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C |
φ |
C3 |
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A1 |
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A3 |
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φ1 |
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C1" |
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SECTION 1 |
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SECTION 2 (HIGH Q) |
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C2 |
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C1 |
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C3 |
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A4 |
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A5 |
Vout |
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φ1 |
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C1"
Thought the same procedures, we have CA 17.666,CB 7.7286 C1 1.9926,C2 =1
C3 2.1116,C4 = 2
C1" 6.3085
5 Final Design
Cmin is chosen as 0.5pF => C=1
op amp: gain 70dB bandwidth 3 MHz passband sensitivity to capacitance variation
§14-12.2 Bilinear Ladder SCF Design
1. The same filter specification.
Elliptic ladder filter is chosen(fifth-order). The result is
14-62 CHUNG-YU WU
4.Scaling
1)Vp1=occurs at dc where H0(1)=-CS/CD=-21.345
(1)We want an overall passband gain of 1. =>Ho(1)→-1 => CD=CS=2, CE 19.345, C1"20.672, C2 12.518
(Multiplying all capacitors connected or switched to the output node of op-amp A1 by 21.345)
(2)All capacitors at the input node of A1 should be scaled so that the
smallest (Cs |
2 |
) equals 1. (O.K.) |
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2)Vp2 (peak output voltage of op-amp A2) occurs around fp2=1.10kHz
(1)Vp2 177.05 for Vin=1
Reducing Vp1/Vin to 1
=>CA and C3 are multiplied by 177.05=> CA 177.05, C3 24.424.
(2) Vp3 180.80 at 1.07kHz
=>CB,C2, and C4 are multiplied by 180.80=>CB 180.80, C2 24.941, C4 41.354.
(3)Minimize total capacitance=>C1, C2, C4, and CA at the input node of op-amp A2 are scaled to make C1=1
=>C1=1, C2 1.9926, C4 3.3036, CA 14.144
(4)Similarly, C1"=1, C3 1.1815, CB 8.7466. (The input of A3)
3)Vp4 503.57 and Vp5 230.14
0.2dB/1%
14-63 CHUNG-YU WU
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RS |
L2 |
L4 |
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Vin |
C1 |
C2 C3 |
C4 |
C5 |
RL |
Normalized component values:
Rs=RL=1 C1=0.85535 C2=0.15367 L2=1.20763 C3=1.48438 C4=0.46265 L4=0.89794 C5=0.63702
ŵap=1 rad/s
2. Frequency prewarping and denormalization
ω |
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2 |
tan |
ωpT |
= 2 f |
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tan |
πf p |
6291.4667rad / s |
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2 |
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ap |
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T |
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c |
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fc |
Multiplying each resistor by z0, each inductor by L0=z0/ωap, and each capacitor by C0= 1z0 ωap. 50Ω
Usually choose z0=real source and termination resistance 100Ω 600Ω
Here, C0=1 is chosen => z0= |
1 |
and L0= |
1 |
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ω |
ap |
ω |
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ap |
We have the denormalized element values as:
C1=0.85535, C2=0.15367, L2=1.20763×Lo=3.05090×10-8,
C3=1.48438, C4=0.46265, L4=0.89794×Lo=2.26851×10-8,
C5=0.63702, Rs=RL=z0=1.58945×10-4
3. SC realization
Using the exact design technique of SC ladder filter (Section 14-10), the state equations are
-V = − |
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1 |
( |
1 |
(V |
−V ) − I |
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+ sC' |
V ), |
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in |
1 |
2 |
3 |
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sC'1 RS |
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-I2=-( |
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1 |
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− sCL2 ) (V1 V3), |
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sL2 |
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V3= |
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(−I2 − sC'2 V1 − sC4 'V5 + I4 ), |
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sC'3 |
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14-65 |
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4.Scaling |
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CHUNG-YU WU |
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Vin=1V, we have: |
Vp1 0.92V, |
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C1=1.00000 |
C05=1.14172 |
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A1: CA,C2,C21, and C02 |
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Vp2 |
34V, |
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C2=1.83854 |
C06=1.52861 |
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multiplied by Vp1 |
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Vp3 |
0.764V, |
C3=2.00000 |
C07=2.02212 |
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A2: C3,C01, and C03 |
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Vp4 |
28.86V, |
CA=13.87171 |
C08=1.00000 |
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multiplied by Vp2 |
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Vp5 |
0.5V, |
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C01=1.77112 |
CE=8.27441 |
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C02=1.20275 |
CD=14.43078 |
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C03=1.00000 |
CL=1.00000 |
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C04=1.00000 |
C41=2.09575 |
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CB=11.11901 |
C42=5.67396 |
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for dynamic range scaling |
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Cc=14.46156 |
C21=1.29480 |
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C22=1.90667 |
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minimum-capacitance scaling: |
Cs |
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CA |
2 |
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5.Final design
Cmin , OP amp: 70dB 3 MHz
=>Passband ripple: 0.06dB minimum stopband loss 39.5dB
Maximum sensitivity: 0.05dB %
§14-12.3 LDI Ladder SCF Design
1. LCR prototype circuit
Fifth-order elliptic LC ladder filter with the same lowpass specifications.
2. Frequency prewarping and denormalization ωap ωp (for simplicity)
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z0=1Ω => C0= 1 |
3 |
) |
F, L0= |
1 |
H |
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(2π103 ) |
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(2π10 |
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The denormalized element values:
Rs=1Ω,
C1=136.13318µF, C4=73.633034µF, C2=24.45734µF, L4=142.91159µH, L2=192.20028µH, C5=101.38488µH, C3=236.24641µF, RL=1 Ω.
State equations: |
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−V1 +Vin + sC V |
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-V = |
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− I |
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s(C |
+C |
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1 |
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Rs |
2 3 |
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-I2= V3 −V1 , |
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sL2 |
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V3= − s(C2 +C3 +C4 ) ( − I2 − sC2V1 − sC4V5 + I4 ), |
I4= V3 −V5 , |
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sL4 |
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s(C4 |
1 |
(I4 |
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V5 ). |
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RL |
14-66 CHUNG-YU WU
3.SCF design
The flow diagram is shown on P.14-? whereas the active-RC circuit is given on P.14-?.
The SCF is shown on P.14-? where T=20µs is chosen and the component values are
C1+C2=160.59µF, |
C2+C3+C4=334.34µF, |
CS= |
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=20µF, |
C4+C5=175.018µF, |
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C= |
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CL= |
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RL |
4.Scaling
Dynamic range scaling with Vpi listed: followed by minimum-capacitance scaling
Element values: |
SCF: |
C1=8.03214, |
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C3=12.97271, |
C1A=1, |
C3A=1.08390, |
C1B=1.07930, C3B=1, |
C1C=1.29263, C3C=1.02540, |
C1D=1.13212, C3D=1.66885, |
C2=13.42236, C4=15.76379, |
C2A=1.08053, C4A=1.71203, |
C2B=1, |
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C4B=1, |
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C5=8.75121, |
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C5A=2.20614, |
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C5B=1, |
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C5C=6.29664. |
5.Final design
Cmin Passband ripple: 0.095dB>0.044dB Minimum stopband loss: 40.5dB OP amp: 70dB, 3MHz
Maximum passband sensitivity: 0.08dB
%
for A1:Vp1=0.927 V at 1.182kHz. for A2:Vp2=1.198 V at 1.121 kHz. for A3:Vp3=0.857V at 1.061 kHz. for A4:Vp4=1.105 V at 1.061 kHz. for A5:Vp5=0.501 V at 967 kHz.
14-67 CHUNG-YU WU
§14-13 Nonideal Effects in Switched-Capacitor Filters
1. Switch Turn-On Resistance
The turn-On resistance of a MOSFET can be written as
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Ron= |
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uco |
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w |
(VG S |
−VT ) |
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L |
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* Nonlinear behavior |
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signal voltage -Vss |
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The Ron effect on the simple SC integrator:
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C2 |
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φ 2 |
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+ |
Vout |
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t=nT t=(n+1)T
C2
φ1
R1 R2
-φ2
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C1 |
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Vout |
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t=nT |
nT+T/2 (n+1)T |
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- Vin |
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At t=nT , V1(t)=V1(nT)=Vin(nT)(1-e −T
2R1C1 )
Assume φ1 |
and φ2 are activated for T |
2 |
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∆Q (nT+ |
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2 |
Let R1=R2=R |
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C C |
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Ideal: |
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H(z)=- |
C1 C2 |
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14-68 CHUNG-YU WU
Error: ε=1-(1-e −T / 2RC1 )2 2e −T / 2RC1
Usually ε<0.1%(cap. ratio error) is acceptable.
2e −T / 2RC1 ≤10−4
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=> |
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=RC1fc ≤ |
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0.05 |
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2ln 20000 |
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or RC1 ≤ 20T (= 201fc)
fc=500KHz, C1=5pF R ≤ 20KΩ ; fc=100MHz, C1=2pF, R ≤ 250Ω?
2.Clock Feedthrough Noise
*All switches directly connected to the integrating node generate clock feedthrough noises.
φ2 
n
T
* All clock feedthrough noises are proportional to the sampling frequency. They may have a dc component.
* As soon as the clock feedthrough error voltage does not
14-69 CHUNG-YU WU
saturate the OP AMP, it can be eliminated at the output by reconstruction filters(LPF).
* The dc component cause offset voltage problems.
3.Junction Leakage
* Worst-case (100°C or 125°C) leakage at the integrating node: ~10 nA/mil2 5µm×5µm junction => 400 pA leakage
*fs, max is about 25KHz in this case to avoid significant errors.
*The leakage cause dc offset voltages.
4.DC offset Voltage of the OP AMP
+
pratical op amp
C2
φ2 φ2
-
C1 +
+
-
Voff
+
+ ideal op amp
-
Voff Voff = 5~20mv
Vout
* Vout=(1+ C1 ) Voff
C2
*Integrator-based design may have a dc offset problem if no other negative feedback paths exist.
*Too-low-frequency operation is not good.
C2
5. Finite Gain of the OP AMP. |
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Vout(nT)=Vc2(nT)- |
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Vout |
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V |
(z) |
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−(C |
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]−1 z |
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=>H(z)= |
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out |
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= |
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2 |
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Vin (z) |
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z −(1 + 1 |
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