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4. ADC Performance
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§13-6.3 The Proposed A/D Converter
1.Parallel processing with two 8-bit subconverters. (Time-interleaved ADC)
2.Two-step structure with single resister ladder.
3.Using 31 dynamic coarse and 15 fine comparators for 3V Vdd design. (No op amps is required)
4.1-bit digital error correction.
ŸThe proposed A/D converter with parallel processing architecture.
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Ÿ The proposed 8-bit A/D subconverter.
Ÿ The timing diagram of a 8-bit A/D subconverter.
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Ÿ The circuit of the coarse comparator.
Ÿ Fine comparator and its clock sequences.
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Ÿ Intermeshed resistor reference ladder.
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Ÿ The layouts and their equivalent circuits (a) with and (b) without separated unit resistors.
(a) |
(b) |
Experimental Results:
Ÿ Chip photograph of the fabricated A/D converter.
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Ÿ A typical plot of the differential nonlinearity.
Ÿ A typical plot of the integral nonlinearity.
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Ÿ The FFT spectrum for a 85 KHz sine-wave input signal
Ÿ The effective bits versus input frequency characteristics.
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Table 1 Major characteristics of the A/D converter.
Process: |
0.8μm CMOS |
Resolution: |
8bits |
Differential nonlinearity: |
-0.4 to + 0.4 LSB |
Integral nonlinearity: |
-0.6 to + 1 LSB |
SNDR(for 85KHz input): |
46.8 dB |
Sampling rate: |
50 MHz |
Input dynamic range: |
0.5V to 2.5V |
Power supply: |
3V |
Power dissipation: |
100 mW |
Active area: |
4950 um × 3790 μm |
|
|
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§13-7 Pipelined (Multistage) ADC
uNeed m(2N/m-1) comparators R tapes.
uNeed m op amps for S/H subtractors.
² High-performance op amp is not easy to be achieved (especially for 3V Vdd).
Block diagram of a pipelined A/D converter