*Compatible with all MOS technologies.
2.MOS capacitor
metal
thin oxide
p+
P-sub
*Realizable only by NMOS and CMOS metal-gate technology.
*TC=25 ppm/oC Tolerance=±15% VC=25ppm/V
*Voltage-dependent capacitance
accumulation depletion
3. Poly (or metal ) to bulk silicon capacitor
Poly Si
Metal
Thin thermal oxide |
Heavy n+ implant |
P
*Realizable by NMOS and CMOS poly-Si-gate (metal-gate ) technologies.
+
* Need an extra mask to define the heavy n implant as the bottom plate.
* Can be trimmed by laser on poly-fuse. ( Poly-fuse : blown with 10-20mA )
* Bottom plate pn junction parasitic capacitance (≈ 15% − 30% ) * VC of the capacitor≈ -10ppm/V
9 - 5
* TC ≈ 20-50 ppm/oC |
CHUNG-YU WU |
*Tolerance ≈ ±15%
4.Poly to field implant region capacitor
poly-Si
field oxide
n+ 
p+
substrate
p-sub
*Realizable only by NMOS and CMOS Si-gate technologies with the field implant.
*Smaller oxide capacitance per unit area
Thick field oxide
*The capacitor’s bottom plate must be always connected to the substrate.
*Low quality dielectric oxide.
5.Metal to poly capacitor
metal |
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poly oxide |
poly |
CThick |
CB |
Thick oxide |
P-sub
*Realizable by NMOS and CMOS Si-gate technologies.
*Interdielectric is poly-oxide.
*Extra mask to define the ploy-oxide pattern.
*Poly fuse trimming is possible.
*CVD oxide is not good as capacitor dielectric
9 - 6
CHUNG-YU WU
hysteresis in Q-V due to dielectric changing and
relaxation.
*For reliability consideration, the top metal layer must be larger than the poly oxide layer.
ÞCThick exists
Þparasitic capacitance
*VC=100ppm/v, TC=100ppm/oC
6.poly to poly capacitor
CB
poly to substrate parasitic cap.
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deposited |
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oxide |
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Poly 1 Field oxide
P
*Realizable by NMOS and CMOS double-poly technologies.
*VC=100ppm/v TC=100ppm/ oC
*Double-poly
Þ EPROM or E 2 PROM are available
Þ may be applied in trimming
* The poly2 area may be smaller than the poly-oxide area
Þ small CThick
General Reference: D. J. Allstot and W. C Black, Jr., IEEE Proc. vol-71, pp967-986, 1983.
§ 9-3 Tolerance Considerations.
Resistors : Absolute tolerance ≈ ±20% ~ ±40%
Matching or ratio tolerance ≈ ±0.1% ~ ±10%
Capacitors: Absolute tolerance ≈ ±15%
Matching or ratio tolerance
Resistors :
9 - 7
≈ ±0.01% ~ ±1% |
CHUNG-YU WU |
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If L is large Þ |
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ρ L |
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æ |
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R = |
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σ R = |
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δW |
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for |
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* Long resistor pattern is recommended in precise resistors. |
Capacitors: |
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C = |
ε sio 2 |
WL |
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ε si02 |
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ε sio 2 |
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tox |
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edge effect |
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Oxide effect |
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CASE I : Absolute tolerance |
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L |
(if W and L are small or |
εsio 2 and |
tox are |
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neglible) |
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If W and |
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= σl |
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σ |
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W 2 |
L2 |
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Assume L=W=d , |
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σ C |
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l |
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is minimum |
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Þ σ C |
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square( L=W ) < σ C |
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non -square( W ¹L ) |
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For the same WL ,minimum perimeter leads to minimum telerance.
Circular shape?
CASEII : Ratio or Matching tolerance under geometry random variation
9 - 8
α º |
C1 |
= |
W1 L1 |
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dα |
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dC1 |
- |
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dC2 |
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CHUNG-YU WU |
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C2 |
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W2 L2 |
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α C1 |
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C2 |
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σ dα = σ dc |
2 +σ dc |
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2 =σl |
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σ |
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d |
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Þ σ dα |
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σ l |
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if |
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αd |
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square versus square
CASE III : Ratio tolerance under the uniform undercut effect Uniform undercut is not a random variation.
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α º |
C1 |
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W1 L1 |
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C2 |
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d 2 |
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W L - P x + 4 x 2 |
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W L - P x |
α |
actual |
= |
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1 1 |
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1 |
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@ |
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d 2 - P x +4 |
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x2 |
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2 - P |
x |
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α |
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x |
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P |
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@ |
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( P - |
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d 2 |
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P |
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2( W + L ) |
IF |
P = |
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Þ |
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α @ 0 |
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i.e. 4d = |
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α |
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So |
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W1 L1 =αd 2 |
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ü |
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2( W1 + L1 ) = 4dα |
ý |
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þ |
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ÞW |
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= d( α - α 2 -α ) |
L = d( α + α 2 -α ) (2) |
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1 |
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σ |
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2 α >>1 σ |
l |
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σ dα = |
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6 - |
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6 |
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d |
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If α =1 , both conditions(1) and (2) can be satisfied
Þ Ratio tolerance ¯
9 - 9
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CASE IV : Ratio tolerance under edge and oxide effects |
CHUNG-YU WU |
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Take |
α =1 |
Þ unit capacitor array |
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D |
D |
D |
D |
D |
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D |
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D |
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C1 |
= 4 |
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C |
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2 |
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C2 |
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D |
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D |
: Dummy capacitor |
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pattern |
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*Centralized structure to avoid the oxide effect.
*Dummy capacitor may be omitted to save area.
*Ratio tolerance can be ±0.06 %
Similarly, for resistors, we have
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R2 |
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R1 |
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R2 |
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dummy |
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dummy |
resistor |
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resistor |
* Ratio tolerance can be ±0.25 %
§9-4 The MOS Switch
1.The NMOS switch
1)If Vφ³V1+VTHN , MN on Þ V2=V1 full transimission
9 - 10
CHUNG-YU WU
Vφ
Example:
V1= 0V, Vφ= 3V Þ V2= 0
V1= 5V, Vφ= 8V, VTN =1.5V Þ V2= 5V 2) If V1 +VTHN >Vφ >VTHN , MN on
V2 =Vφ -VTHN |
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Example: Vφ |
= 5V , |
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V1 = 5V , |
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VTHN = 1.5V (under substrate |
bias), VBS = 0V |
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ÞV2 = 3.5V |
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3) If Vφ <VTHN , |
M N off |
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Node 1 or 2 may be floating |
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Þ V1 or V2 |
will be gradually charged or discharged by the |
leakage current in |
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MOS or PN junctions. |
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Vφ |
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n+ |
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p |
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If V = 0V |
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A |
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→ 0V by the n + p |
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time, V |
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for a |
very long |
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A |
φ |
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junction leakage current Þ Not allowable in circuit design
*When the switch is turned on or off, the charging or discharging current is nonlinear Þ Nonlinear resistor
Capacitance feedthrough effect:
* Can’t pass low voltage completely.
Example: Vφ = 0V , V2 i = 5V , V1 =0V , VTP = 1.5V
ÞV2 f »1.5V ¹ 0V
3. The CMOS switch
Vφ
Vφ
*Full transmission
*The clock feedthrough effect can be greatly compensated, if
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the delay between Vφ |
and |
V− |
is zero. |
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φ |
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Nonlinear Cgs and |
Cgd |
and |
the delay between Vφ and |
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V− |
make the compensation of the feedthrough effect quite |
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φ |
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complicated. |
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* |
If |
V1 = 5V =Vφ ,V_ = 0V ,VDD = 5V ,VTN =|VTP |=1.5V |
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φ |
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V2 = 0V ®V2 = 5V -1.5V = 3.5V : NMOS and PMOS |
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V2 |
= 3.5V ®V2 = 5V : Only PMOS |
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If V1=0V, V2i=5V |
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V2 = 5V → V2 = 1.5V : NMOS and PMOS |
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V2 = 1.5V ®V2 =0V : Only NMOS |
10 - 1
CHUNG-YU WU
Chapter 10 CMOS Bandgap References
§10-1 Basic Principles of Bandgap References (BGR)
VBE (on ) = mVtherm ln( I1 / IS )
I |
S |
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= qAn |
2 |
D |
/ Q |
B |
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I |
S |
:Reverse saturation current of a BJT |
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i |
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= Bni |
2 |
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A :Area of a BJT |
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D |
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= B 'ni |
2T |
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QB :Base minority carrier charges |
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μ |
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where B and B' are |
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: Average diffusivity of carriers |
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D |
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constants, indep. of T. |
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= CT − n |
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C:Constant, indep. of T. |
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μ |
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n:Temp. exponent. |
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n 2 = ET 3 |
exp(-V |
/V ) |
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E : Constant, indep. of T. |
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i |
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GO |
therm |
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VGO : Energy gap.
= mVtherm ln[I1T −γ F exp(VGO /Vtherm )]
F :Constant , indep. of T.
γ = 4 - n
where I1 is the collector current and
G is a temp.-indep. constant.
Þ VBE (on ) = VGO -Vtherm [(γ -α) ln T - ln(FG )]
In general, the output voltage |
Vout |
is a sum of VBE (on ) , and KVtherm with a |
weighting factor K such that |
Vout |
is nearly indep. of T. |
VBE (on ) + KVtherm = Vout = VGO - mVtherm (γ -α) lnT + mVtherm [K + ln(FG )] …………(1)
dVout |
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= 0 = |
mVthermo |
[K + ln(FG )]- |
mVthermo |
(γ -α) lnT |
- |
mVthermo |
(γ -α) + |
d |
V |
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dT |
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T =TO |
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TO |
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TO |
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O |
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TO |
dT |
GO |
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TO |
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æ d |
ö |
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Þ K + ln( FG) = (γ -α) lnTO |
+ (γ -α) - ç |
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VGO ÷ |
× |
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…..(2) |
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è dT |
ø |
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mVthermo |
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Substituting (2) into (1) , we have
Vφ