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4.Measurement results DNL:
INL:
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Spectrum:
SNR & THD
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A folding block with a folding-rate of four. (a) A possible single-ended circuit realization; (b) input-output response.
*4-bit folding ADC architecture: MSB 2-bit: flash
LSB 2-bit: folding
LSB: V1, V2, V3, and V4 produce a thermometer code for each of the four MSB regions.
* Examples: Vin: |
0 ® 1/4 V |
Thermometer code: 0000, 0001, 0011, 0111, 1111 |
|
Vin: |
1/4 V ® 1/2 V |
Thermometer code: 1110, 1100, 1000, 0000
*Total number of latches: 8
as compared to 16 in flash ADC.
*No S/H is required.
*Folding blocks realized by BJT cross-coupled differential pairs as an example.
*Large input capacitance seen by Vin.
*The output signal frequency = input signal frequency ´ folding rate Þ limits the practical folding rate used in high-speed converter.
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§13-8.3 Folding and Interpolating ADC
A 4-bit folding A/D converter with a folding rate of four and an interpolate-by-two. (The MSB converter would usually be realized by combining some folding-block signals.)
* Folding rate: 4; |
Interpolation: 2 |
*V4 is a new inverted signal from V4.
*Latch number ↓ Input capacitance ↓
*Capable of > 100 MHz operation.
*Can be implemented in CMOS.
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§13-8.4 A 400-Ms/s 6-bit CMOS Folding and Interpolating ADC
Ref.: IEEE JSSC, vol. 33, no. 12, pp. 1932-1938, Dec.1998
1.The structure of a folder with differential outputs.
*A practical folder has 5 amplifiers.
2. A 3-bit folding converter and its cyclic code:
*Folding rate N, full-scale sinusoid
ÞFolded signal frequency
»π2 N×frequency Fin
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3. The block diagram of the 6-bit converter
Fig. 5 Block diagram of the 6-bit converter
4. The folder structure:
*Folding rate: 4 Interpolation: 2
*16 comparators and 16 folders → cyclic thermometer → 5 LSBs.
*5 amplifiers are used
*Two stages → higher gm.
*Resistor load → better transient performance.
*Output current mode → speed −.