Micro-Cap v7.1.6 / RM

What's in this chapter

This chapter describes the Micro-Cap digital simulator. It begins with a general description of the digital simulation engine, delay models, digital states and strengths and then describes each of the digital primitives. The primitives are the basic building blocks used to model standard commercial parts. They are used extensively as modeling elements in the Digital Library. They may also be used as primitives in schematics or SPICE circuits.

This chapter discusses:

The digital simulation engine

Digital nodes

Digital states

Digital strengths

Timing models

Propagation delay

Digital primitives

The Analog/digital interface

Digital stimulus devices

Digital input D/A interface device

Digital output A/D interface device

Standard gates

Tri-state gates

Flip-flops and latches

Delay lines

Pullup and pulldown devices

Programmable logic arrays

Multi-bit A/D and D/A converters

Digital behavioral functions

Logic expressions

Pin delays

Constraint checkers

Stimulus generators

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The digital simulation engine

Micro-Cap includes a general purpose, event-driven, digital logic simulator. It is completely integrated within and time-synchronized with the analog simulator.

The primitives and behavior of a digital simulator can be defined in many ways. Micro-Cap uses the PSpiceTM syntax since it is relatively efficient, widely known, and for many users, it means not having to relearn a new system. Micro-Cap and PSpiceTM libraries can be read by either simulator, so portability between the two is improved as well. PSpiceTM can't read Micro-Cap schematics, but it can read the Micro-Cap SPICE text circuit files. Micro-Cap can read most PSpiceTM text circuit files. Most, but not all, features are supported.

Micro-Cap schematics and SPICE text file circuits may freely mix analog and digital circuits. The system automatically handles the interface between the analog and digital sections. Whenever analog and digital parts share the same node, MC7 automatically breaks the connection and inserts a user specified interface circuit between the two sections. The heart of the interface is an analog to digital interface translator (if the digital node was an input) or a digital to analog translator (if the digital node was an output). This automatic A/D interface is described in more detail later in the "Analog/digital interface" section of this chapter.

Digital nodes

Digital nodes are represented the same way as analog nodes. They may be referred to by node number or node name. Nodes are numbered automatically by MC7. Node names are assigned by the user by placing grid text on the node.

Digital node numbers are displayed on schematics inside sharp-cornered rectangles to reflect the angular look of digital waveforms. Analog node numbers use round-cornered rectangles to reflect the softer nature of analog waveforms.

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Digitalstates

The state of a digital node is a combination of a digital level and a digital strength. Together the digital level and digital strength uniquely determine the digital state. The state is represented with one of the following symbols:

Table 23-1 Digital states

Logic levels

These six symbols are used to describe what is happening on the digital nodes. The first five symbols, { 0, 1, R, F, X } describe logic levels at any strength greater than the high impedance strength. The 'Z' symbol describes any of the levels at the high impedance strength.

If a node state symbol is 'Z', then the strength of the output node is equal to the high impedance or 'Z' state. If the symbol is a '1', then the state is steady at a high level. If the symbol is a '0', then the state is steady at a low level. If the symbol is an 'R', then the state is rising to a '1'. If the symbol is an 'F', then the state is falling to a '0'. If the symbol is an 'X', then the state may be '0', '1', or unstable.

Logic levels correspond to a particular range of voltage, as defined in the I/O model statement. They do not correspond to a particular value of voltage. For instance, a '1' may be defined in the model statement as the voltage range 1.7 to 7.0 volts. If the digital node makes a transition between a '0' and a '1' then the implied analog voltage may be said to be "at least 1.7 volts", but it may be higher. Digital modeling involves an abstraction that trades information in exchange for simplicity and speed of simulation.

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During the simulation run, each output is assigned the DRVH or the DRVL strength based upon its current state.

DIGOVRDRV, DIGDRVF, and DIGDRVZ are specified in the Global Settings dialog box and can be changed for a particular circuit with the .OPTIONS command.

Tri-state outputs

A common situation where multiple strengths help in modeling is the tri-state bus. In this situation many tri-state devices are connected to a common node. Each has an enable pin. If the enable pin is disabled, the output impedance is DIGDRVZ and the strength is 0. Typically, all outputs but one will be disabled and their strengths will be 0. One output will be enabled and its strength will be greater than 0 and hence the output state will be determined by the one enabled output. It is important to remember that the DRVH or DRVL of the enabled output must still exceed the DIGDRVZ by DIGOVRDRV to control the node state.

Open-collector outputs

Another situation where multiple strengths help is in the modeling of open collector outputs. In this situation, many devices are connected to a common node. Each might typically have impedances of DRVL=100 and DRVH = 20K. A single PULLUP device is connected to the common node. It provides a weak '1' of typically 1K. If any output is a '0', then its strength is sufficient to overcome the weak PULLUP '1' strength (1K) and the even weaker 'Z' strength (20K) of the other output devices. The output becomes a '0'. If all outputs are at a '1' at Z strength (20K), then the PULLUP provides a '1' at higher than Z strength and the output goes to a '1'.

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Unspecified propagation delays

The timing model syntax provides minimum, typical, and maximum values for each propagation delay parameter. The names of these parameters always begin with 'TP'. Data books often specify only one or two of these parameters. Since the logic simulator can't just assume a default value of zero for unspecified parameters, it calculates them according to the following rules:

If the typical value is specified:

If the minimum value is unspecified:

TPXXMN = DIGMNTYSCALE • TPXXTY

If the maximum value is unspecified:

TPXXMX = DIGTYMXSCALE • TPXXTY

If the typical value is not specified:

If the minimum and maximum values are both specified:

TPXXTY = (TPXXMN + TPXXMX) / 2

If only the minimum value is specified:

TPXXTY = TPXXMN / DIGMNTYSCALE

If only the maximum value is specified:

TPXXTY = TPXXMX / DIGTYMXSCALE

If none of the values are specified, then obviously:

TPXXMN = TPXXTY = TPXXMX = 0

Default values of the parameters DIGMNTYSCALE and DIGTYMXSCALE are specified from the Global Settings dialog box. The default value is used unless it is changed in a particular circuit with the .OPTIONS command. For example:

.OPTIONS DIGMNTYSCALE=.35

Placing this command in a circuit changes its DIGMNTYSCALE value only.

Note that these rules apply only to propagation delay parameters.

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Unspecified timing constraints

Timing constraints include pulse widths and setup and hold times. Typical and maximum values for these timing constraints are frequently missing from data books. Unlike propagation parameters, these missing values cannot be obtained by a simple scaling procedure. Instead, the simulator calculates the missing values according to the following procedure:

If the minimum value is not specified: minimum = 0

If the maximum value is not specified:

If the typical value is specified: maximum = typical

If the minimum value is specified: maximum = minimum

If the typical value is not specified: typical = (maximum + minimum)/2

Note that a parameter is unspecified if it is missing from the model statement. For example, a model statement with unspecified parameters looks like this:

.MODEL TOR UGATE ( )

Another approach is to include the unspecified parameters and set them equal to the special value, -1, as a way of signalling to the generation routines that they are to be considered unspecified. This form of model statement looks like this:

.MODEL TOR UGATE ( TPLHMN=-1 TPLHTY=-1 TPLHMX=-1 + TPHLMN=-1 TPHLTY=-1 TPHLMX=-1 )

Any parameter set equal to -1 is treated as unspecified and thus calculated from the other parameters according to the above rules. Having the names of unspecified parameters readily available is a convenient memory aid in case they need to be modified. MC7 generates default model statements in this form.

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Propagation delays

Loading delays

The propagation delay through a digital device is specified mainly in the timing model through the propagation delay parameters. The I/O model can also affect the propagation delay through the loading delay. The two loading delays (low to high and high to low) are calculated from the capacitive loading on the node prior to the simulation run. The capacitive load is derived from the I/O models for the devices that are connected to the node. The total capacitive load is obtained from the sum of all INLD values from devices whose inputs are connected and OUTLD values from devices whose outputs are connected. The total capacitive load is assumed to be driven by the device's driving impedances, DRVH or DRVL. The two loading delays are calculated for each device as follows:

Loading delay low to high= ln(2)•DRVH•CTOTAL

Loading delay high to low= ln(2)•DRVL•CTOTAL

During the simulation, one of these delays, depending upon the transition, is added to the timing model delay when an event is scheduled.

Inertial delays

Micro-Cap models all delays except those of the DLYLINE on the inertial model. Inertial delay models work on the physical principle that a signal must be impressed upon a device for a certain minimum time before the device will respond. The principle can be summarized as follows:

If the pulse width is less than the delay the pulse is cancelled.

In this circuit, the pulse width is 10. That is greater than the delay of 5, so the pulse will pass:

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In this example, the pulse width is 2. Since that is less than the specified delay of 5, the pulse is inertially cancelled.

Inertial cancellation can be turned off from the Preferences dialog box.

Transport delays

The alternative to inertial delay is transport delay. In this delay model, all signals

are passed, regardless of the pulse duration. For example, this circuit passes all pulses, even though they are less than the specified delay.

This type of delay is useful when you want to shift a signal by some fixed delay value without removing any of its narrow pulses. Only the DLYLINE device uses transport delay. All delay parameters of all other devices are treated as inertial, except when inertial cancellation is disabled.

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