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I/O model

I/O models provide the information necessary to determine the output strength when devices are wire-ored together, and to create the interface circuits when the digital part is connected to an analog part.

I/O models capture the electrical information common to the IC technology and circuit techniques used to design and build them. Thus, a typical digital family will have only four or five I/O models. The only difference in the I/O models within a digital family is to account for the different circuits employed at the input or output, as, for example, in open-collector outputs and Schmitt-trigger inputs.

I/O model format

.MODEL <I/O model name> UIO ([model parameters])

Parameter

Description

Units

Default

 

 

 

 

INLD

Input load capacitance

farad

0

 

 

 

 

OUTLD

Output load capacitance

farad

0

 

 

 

 

DRVH

Output high level resistance

ohm

50

 

 

 

 

DRVL

Output low level resistance

ohm

50

 

 

 

 

DRVZ

Output Z state resistance

ohm

250K

 

 

 

 

INR

Input leakage resistance

ohm

30K

 

 

 

 

TSTOREMN

Min storage time for charge storage node

sec

1E-3

 

 

 

 

AtoD1

AtoD interface circuit for level 1

 

AtoDDefault

 

 

 

 

DtoA1

DtoA interface circuit for level 1

 

DtoADefault

 

 

 

 

AtoD2

AtoD interface circuit for level 2

 

AtoDDefault

 

 

 

 

DtoA2

DtoA interface circuit for level 2

 

DtoADefault

 

 

 

 

Table 23-22 I/O model parameters

587

Parameter

Description

Units

Default

 

 

 

 

AtoD3

AtoD interface circuit for level 3

 

AtoDDefault

 

 

 

 

DtoA3

DtoA interface circuit for level 3

 

DtoADefault

 

 

 

 

AtoD4

AtoD interface circuit for level 4

 

AtoDDefault

 

 

 

 

DtoA4

DtoA interface circuit for level 4

 

DtoADefault

 

 

 

 

TSWLH1

Low to high switching time for DtoA1

sec

0

 

 

 

 

TSWLH2

Low to high switching time for DtoA2

sec

0

 

 

 

 

TSWLH3

Low to high switching time for DtoA3

sec

0

 

 

 

 

TSWLH4

Low to high switching time for DtoA4

sec

0

 

 

 

 

TSWHL1

High to low switching time for DtoA1

sec

0

 

 

 

 

TSWHL2

High to low switching time for DtoA2

sec

0

 

 

 

 

TSWHL3

High to low switching time for DtoA3

sec

0

 

 

 

 

TSWHL4

High to low switching time for DtoA4

sec

0

 

 

 

 

TPWRT

Pulse width rejection threshold

sec

prop delay

 

 

 

 

DIGPOWER

Power supply subcircuit name

 

DIGIFPWR

 

 

 

 

Table 23-22 I/O model parameters (continued)

INLD and OUTLD are used to compute the optional loading delay. This value increases the propagation delay through the device to account for excessive capacitive loading on the node caused by high fan-out. Fan-out is the number of gate inputs connected to a device's output.

DRVH and DRVL are the high state and low state impedances used to determine output strength. Strength is used to resolve the output state when a digital output is connected to other digital outputs.

DRVZ, INR, and TSTOREMN are used to determine which nodes are to be treated as charge storage nets. Charge storage nets are not available in the current version.

AtoD1 through AtoD4 and DtoA1 through DtoA4 supply the names of the interface circuits. INLD and the AtoD names do not apply to stimulus sources since

588 Chapter 23: Digital Devices

they do not have inputs. Refer to the "Analog/digital interface" section for more information.

The switching times TSWLH1... TSWLH4 and TSWHL1...TSWHL4 are subtracted from the digital device's propagation delay on outputs which are connected to analog devices. The purpose is to compensate for the time it takes the DtoA interface circuit to switch. By compensating in this way, the analog signal at the other side of the DtoA interface should reach the switching level just when the digital device does at the stated delay. The values for these switching delays are determined by attaching a nominal load to a digital output, and measuring the switching time. If the switching time is greater than the stated delay, a delay of zero is used. These parameters are used only when analog nodes are connected to digital outputs.

The DIGPOWER parameter specifies the name of the power supply subcircuit to be used when an AtoD or DtoA interface is required. The default value is DIGIFPWR. This power supply subcircuit can be found in the DIGIO.LIB. It is the standard circuit for TTL circuits.

Note that the TPWRT parameter is not included in the current version. It is accepted as a parameter, but not processed.

589

Digital / analog interface devices

When a digital node and an analog node are connected together in a circuit, the system breaks the connections and inserts between the two parts the interface circuit specified in the I/O model. These interface circuits contain analog devices like resistors, capacitors, diodes, and transistors. They also contain either an analog to digital or digital to analog interface device. These devices provide the fundamental translation between the analog and digital circuits.

Digital input device (N device)

When a digital output node is connected to an analog node, the interface circuit requires an N device. Its function is to translate digital levels to analog voltages and impedances to drive the analog node.

SPICE format

N<name> <interface node> <low level node> <high level node> +<model name>

+ DGTLNET=<digital node name> +<I/O model name>

+[IS=<initial state>]

Schematic format

PART attribute <name>

Example

FS1

MODEL attribute <model name>

Example

D0_AD

I/O MODEL attribute <I/O model name>

Example

IO_STD

590 Chapter 23: Digital Devices

IS attribute <initial state>

Example 1

Model form

.MODEL <model name> DINPUT ([model parameters])

Parameter

 

Description

Units

Default

 

 

 

 

 

CLO

 

Capacitance to low level node

farad

0

 

 

 

 

 

CHI

 

Capacitance to high level node

farad

0

 

 

 

 

 

S0NAME

 

State '0' character abbreviation

 

 

 

 

 

 

 

S0TSW

 

State '0' switching time

sec

 

 

 

 

 

 

S0RLO

 

State '0' resistance to low level node

ohm

 

 

 

 

 

 

S0RHI

 

State '0' resistance to high level node

ohm

 

 

 

 

 

 

S1NAME

 

State '1' character abbreviation

 

 

 

 

 

 

 

S1TSW

 

State '1' switching time

sec

 

 

 

 

 

 

S1RLO

 

State '1' resistance to low level node

ohm

 

 

 

 

 

 

S1RHI

 

State '1' resistance to high level node

ohm

 

 

 

 

 

 

.

 

.

 

 

.

 

.

 

 

.

 

.

 

 

 

 

 

 

 

S19NAME

 

State '19' resistance to high level node

ohm

 

 

 

 

 

 

S19TSW

 

State '19' switching time

sec

 

 

 

 

 

 

S19RLO

 

State '19' resistance to low level node

ohm

 

 

 

 

 

 

S19RHI

 

State '19' resistance to high level node

ohm

 

 

 

 

 

 

 

Table 23-23 The N device model parameters

 

 

 

 

 

591

When a digital device output is connected to an analog node, MC7 automatically breaks the connection and inserts the DtoA circuit specified in the I/O model. That circuit always employs an N device, whose function is to translate the digital states to impedance changes on the analog side. The process is described in more detail in the "The analog / digital interface" section in this chapter.

The equivalent circuit of the N device is as follows:

Figure 23-8 N device equivalent circuit

The N device contains two resistors and two optional capacitors. The resistance of the resistors changes in response to changes in the digital input. In a SPICE file, the digital input node is specified by <digital node name>. In a schematic, the digital input node is simply the node associated with the 'Digital' pin of the N device. When this digital input node changes from a '0' to a '1', the value of RHI changes linearly versus time from the '0' state high resistance to the '1' state high resistance. Similarly, the value of RLO changes linearly versus time from the '0' state low resistance to the '1' state low resistance.

The transition from the old resistance to the new resistance is accomplished in a linear fashion over the switching time specified in the DINPUT model for the new state. The output voltage changes from the old level to the new level during the switching time. The output curve looks somewhat like an exponential due to the simultaneous change of the two resistor values. The transition values of resistance for each state are obtained from the DINPUT model. Normally the <high level node> and <low level node> are connected to the voltage sources that correspond to the highest and lowest logic levels. The connection is usually made within the particular DtoA interface circuit called for in the I/O model.

592 Chapter 23: Digital Devices

Digital inputs may be any of the following states {0, 1, R, F, X, Z}. The N device will generate an error message if any state other than these are presented.

The initial condition of the digital input to the N device is determined during the initial operating point calculation. To override this value, you can use the IS command:

IS=<initial state>

The digital input is set to <initial state> at T = tmin and remains there until one of the devices driving the node changes the node's state.

593

Digital output device (O device)

When a digital input node is connected to an analog node, the A/D interface circuit requires an O device. Its function is to translate analog voltages into digital levels on the digital node.

SPICE format

O<name> <interface node> <reference node> +<model name>

+ DGTLNET=<digital node name> +<I/O model name>

Schematic format

PART attribute <name>

Example

FS1

MODEL attribute <model name>

Example

D_AD

I/O MODEL attribute <I/O model name>

Example

IO_STD

When a digital device input is connected to an analog node, the system automatically breaks the connection and inserts the AtoD circuit specified in the I/O model. That circuit always employs an O device. The function of the O device is to translate the analog voltages on the analog side to digital states on the digital side. The exact process is described in more detail in the "The analog/digital Interface" section of this chapter.

Model form

.MODEL <model name> DOUTPUT ([model parameters])

594 Chapter 23: Digital Devices

Parameter

Description

Units

Default

 

 

 

 

RLOAD

Output resistance

ohm

1/Gmin

 

 

 

 

CLOAD

Capacitance to high level node

farad

0

 

 

 

 

S0NAME

State '0' character abbreviation

 

 

 

 

 

 

S0VLO

State '0' low level voltage

volt

 

 

 

 

 

S0VHI

State '0' high level voltage

volt

 

 

 

 

 

S1NAME

State '1' character abbreviation

 

 

 

 

 

 

S1VLO

State '1' low level voltage

volt

 

 

 

 

 

S1VHI

State '1' high level voltage

volt

 

 

 

 

 

.

.

 

 

.

.

 

 

.

.

 

 

 

 

 

 

S19NAME

State '19' character abbreviation

 

 

 

 

 

 

S19VLO

State '19' low level voltage

volt

 

 

 

 

 

S19VHI

State '19' high level voltage

volt

 

 

 

 

 

SXNAME

State to use when the voltage is

 

 

outside all state ranges

 

 

 

 

 

 

 

 

 

Table 23-24 The O device model parameters

The equivalent circuit of the O device is as follows:

Figure 23-9 O device equivalent circuit

595

The O device contains a resistor, RLOAD, in parallel with a capacitor, CLOAD. They are connected between the analog <interface node> and the <reference node>, which is usually analog ground. The analog voltage across the parallel combination is monitored by the O device. The digital output of the O device is the state whose 'State N low level voltage' and 'State N high level voltage' bracket the actual voltage across the parallel RC network. To determine which bracket contains the voltage level, a progressive search is employed. The search starts at the current state bracket. If the voltage is outside the state range, it tries the next highest bracket. If the search fails at state 19, it checks state 0. If this fails, it tries the next highest state. If the entire model is unsuccessfully searched, the system uses the SXNAME if it has been defined. Otherwise it uses the state with the nearest voltage match.

This searching algorithm allows for the easy creation of hysteresis loops. Consider the following model statement:

S0NAME='0' S0VLO=-1.5 S0VHI=1.7

S1NAME='1' S1VLO=0.9 S1VHI=7.0

Suppose the voltage starts at 0.0. The digital level is '0'. As the voltage rises it must exceed the 'S0VHI=1.7' value to exit the '0' state. When it does, it drops into the '1' state. When the voltage starts to decline, it must drop below the 'S1VLO = 0.9' level to drop into the '0' state. This provides a hysteresis value of S0VHI - S1VLO = 1.7 - 0.9 = 0.8 volts. Similar hysteresis values can be designed into the other states.

The state characters used in the model statement must be chosen from the set { 0, 1, R, F, X, Z }. The 'Z' state is usually not used since it conveys no level information and is really just a statement about the impedance level. Other characters will generate error messages and stop the simulation.

596 Chapter 23: Digital Devices

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