MNTYMXDLY attribute <delay select value>
Example 1
IO_LEVEL attribute <interface subckt select value>
Example 1
POWER NODE attribute <digital power node>
Example
$G_DPWR
GROUND NODE attribute <digital ground node>
Example
$G_DGND
Model statement form
.MODEL <timing model name> UTGATE ([model parameters])
Example
.MODEL TRIG UTGATE ( TPLHMN=2ns TPLHTY=3ns TPLHMX=5ns
+ TPZLMN=4ns TPZLTY=6ns TPZLMX=8ns )
The tri-state gate types and their parameters are shown in Table 23-6. The table uses the standard syntax:
en |
one enable node |
in |
one input node |
in* |
one or more input nodes |
out |
one output node |
out* |
one or more output nodes |
517
Type |
Parameters |
Nodes |
Description |
|
|
|
|
BUF3 |
|
in, en, out |
Buffer |
|
|
|
|
INV3 |
|
in, en, out |
Inverter |
|
|
|
|
AND3 |
<no. of inputs> |
in*, en, out |
AND gate |
|
|
|
|
NAND3 |
<no. of inputs> |
in*, en, out |
NAND gate |
|
|
|
|
OR3 |
<no. of inputs> |
in*, en, out |
OR gate |
|
|
|
|
NOR3 |
<no. of inputs> |
in*, en, out |
NOR gate |
|
|
|
|
XOR3 |
|
in1, in2, en, out |
Exclusive OR gate |
|
|
|
|
NXOR3 |
|
in1, in2, en, out |
Exclusive NOR gate |
|
|
|
|
BUF3A |
<no. of gates> |
in*, en, out* |
Buffer array |
|
|
|
|
INV3A |
<no. of gates> |
in*, en, out* |
Inverter array |
|
|
|
|
AND3A |
<no. of inputs>, <no. of gates> |
in*, en, out* |
AND array |
|
|
|
|
NAND3A |
<no. of inputs>, <no. of gates> |
in*, en, out* |
NAND array |
|
|
|
|
OR3A |
<no. of inputs>, <no. of gates> |
in*, en, out* |
OR array |
|
|
|
|
NOR3A |
<no. of inputs>, <no. of gates> |
in*, en, out* |
NOR array |
|
|
|
|
XOR3A |
<no. of gates> |
in*, en, out* |
Exclusive OR array |
|
|
|
|
NXOR3A |
<no. of gates> |
in*, en, out* |
Exclusive NOR array |
|
|
|
|
Table 23-6 Tri-state gate types
The phrase <no. of inputs> is the number of inputs per gate, and the phrase <no. of gates> is the number of gates in an array. Input nodes come first, then the enable node, and then the output nodes. In a gate array, the node order is: input nodes for the first gate, input nodes for the second gate,..., input nodes for the final gate, enable node, output node for the first gate, output node for the second gate,..., output node for the final gate. The number of output nodes is equal to the number of gates. All gates in an array of tri-state gates share a common enable input.
518 Chapter 23: Digital Devices
Parameter |
Description |
Units |
|
|
|
TPLHMN |
Delay: min low to high |
sec |
|
|
|
TPLHTY |
Delay: typ low to high |
sec |
|
|
|
TPLHMX |
Delay: max low to high |
sec |
|
|
|
TPHLMN |
Delay: min high to low |
sec |
|
|
|
TPHLTY |
Delay: typ high to low |
sec |
|
|
|
TPHLMX |
Delay: max high to low |
sec |
|
|
|
TPLZMN |
Delay: min low to Z |
sec |
|
|
|
TPLZTY |
Delay: typ low to Z |
sec |
|
|
|
TPLZMX |
Delay: max low to Z |
sec |
|
|
|
TPHZMN |
Delay: min high to Z |
sec |
|
|
|
TPHZTY |
Delay: typ high to Z |
sec |
|
|
|
TPHZMX |
Delay: max high to Z |
sec |
|
|
|
TPZLMN |
Delay: min Z to low |
sec |
|
|
|
TPZLTY |
Delay: typ Z to low |
sec |
|
|
|
TPZLMX |
Delay: max Z to low |
sec |
|
|
|
TPZHMN |
Delay: min Z to high |
sec |
|
|
|
TPZHTY |
Delay: typ Z to high |
sec |
|
|
|
TPZHMX |
Delay: max Z to high |
sec |
|
|
|
Table 23-7 Tri-state gate timing model parameters
Special Component editor fields
Inputs <number of inputs>
The 'Inputs' field specifies the number of inputs for the gate. When you enter this value, MC7 places an enable pin, an output pin, and the specified <number of inputs> pins on the display and you must drag them into place on the shape.
Flip-flops and latches
Both edge-triggered and level gated flip-flops are provided. Edge-triggered flipflops include the JK flip-flop, JKFF, and the D-type flip-flop, DFF. Both change their state a specified delay time after the active edge of the clock. The active edge of the JKFF is the negative or falling edge. The active edge of the DFF is the positive or rising edge. The gated devices include the set-reset flip-flop, SRFF, and the D-latch, DLTCH. The outputs of these devices follow the input while the gate node is high. The input state sampled during the high state of the gate node is latched and stable during the low state of the gate node. The device is defined as an array of flip-flops, so one or more flip-flops may be instantiated with a single device. The presetbar, clearbar, and clock or gate nodes are common to all flip-flops in the array.
Initialization
Flip-flop devices may be initialized to a particular state by using
DIGINITSTATE. The flip-flop true outputs are set according to this table:
DIGINITSTATE |
Flip-flop Q output |
0 |
0 |
1 |
1 |
All other values |
X |
DIGINITSTATE is set in the Global Settings dialog box. It can also be changed for a particular circuit with the .OPTIONS command.
X-levels
X states are not propagated to the output if the logic precludes that from happening. For example, if clearbar = X, and Q = 0, the Q stays at 0, since both clearbar possibilities (clearbar = 0 and clearbar = 1) both produce Q=0. Similarly, if clearbar = X, and Q = 1, Q goes to X since the two clearbar possibilities (clearbar = 0 and clearbar = 1) each produce different Q outputs (Q=0 and Q=1).
Timing violations
Timing constraints, specified in Table 23-8 and 23-11, are checked only if the value is not zero. If a constraint is violated, the simulator places a warning message in the Numeric Output window, and in the text file CIRCUITNAME.TNO.
Arrays of flip-flops
Note that arrays of flip-flops or latches are available only for SPICE text circuits or SPICE text subckt libraries. Schematic flip-flops or latches are always singles.
520 Chapter 23: Digital Devices
Edge-triggered flip-flops
Two types of edge-triggered flip-flops are provided, the JKFF and the DFF. Both of these devices change after the active edge of the clock. The active edge of the JKFF is the negative or falling edge. The active edge of the DFF is the positive or rising edge.
SPICE format
U<name> JKFF(<no. of flip-flops>) +<digital power node> <digital ground node>
+<presetbar node> <clearbar node> <clockbar node> +<first j node>...<last j node>
+<first k node>...<last k node> +<first q node>...<last q node> +<first qbar node>...<last qbar node>
+<timing model name> <I/O model name> +[MNTYMXDLY=<delay select value>] +[IO_LEVEL=<interface subckt select value>]
U<name> DFF(<no. of flip-flops>)
+<digital power node> <digital ground node> +<presetbar node> <clearbar node> <clock node> +<first d node>...<last d node>
+<first q node>...<last q node> +<first qbar node>...<last qbar node>
+<timing model name> <I/O model name> +[MNTYMXDLY=<delay select value>] +[IO_LEVEL=<interface subckt select value>]
Examples
U1 JKFF(2) $G_DPWR $G_DGND + PREBAR CLRBAR CLKBAR
+J1 J2 K1 K2 Q1 Q2 Q1BAR Q2BAR
+D0_EFF IO_STD IO_LEVEL=1
U4 DFF(1) $G_DPWR $G_DGND +PREB CLRB CLK
+DIN Q QBAR DLY_DFF IO_ACT
Schematic format
PART attribute <name>
Example
U10
TIMING MODEL attribute <timing model name>
Example 74XX
I/O MODEL attribute <I/O model name>
Example
IO_STD
MNTYMXDLY attribute <delay select value>
Example 1
IO_LEVEL attribute <interface subckt select value>
Example 0
POWER NODE attribute <digital power node>
Example
$G_DPWR
GROUND NODE attribute <digital ground node>
Example
$G_DGND
522 Chapter 23: Digital Devices
Parameter |
Description |
Units |
|
|
|
TPPCQLHMN |
Delay: min preb/clrb to q/qb low to high |
sec |
|
|
|
TPPCQLHTY |
Delay: typ preb/clrb to q/qb low to high |
sec |
|
|
|
TPPCQLHMX |
Delay: max preb/clrb to q/qb low to high |
sec |
|
|
|
TPPCQHLMN |
Delay: min preb/clrb to q/qb high to low |
sec |
|
|
|
TPPCQHLTY |
Delay: typ preb/clrb to q/qb high to low |
sec |
|
|
|
TPPCQHLMX |
Delay: max preb/clrb to q/qb high to low |
sec |
|
|
|
TWPCLMN |
Width: min preb/clrb low |
sec |
|
|
|
TWPCLTY |
Width: typ preb/clrb low |
sec |
|
|
|
TWPCLMX |
Width: max preb/clrb low |
sec |
|
|
|
TPCLKQLHMN |
Delay: min clk/clkb edge to q/qb low to high |
sec |
|
|
|
TPCLKQLHTY |
Delay: typ clk/clkb edge to q/qb low to high |
sec |
|
|
|
TPCLKQLHMX |
Delay: max clk/clkb edge to q/qb low to high |
sec |
|
|
|
TPCLKQHLMN |
Delay: min clk/clkb edge to q/qb high to low |
sec |
|
|
|
TPCLKQHLTY |
Delay: typ clk/clkb edge to q/qb high to low |
sec |
|
|
|
TPCLKQHLMX |
Delay: max clk/clkb edge to q/qb high to low |
sec |
|
|
|
Table 23-8a Edge-triggered flip-flop timing model parameters
Model statement form
.MODEL <timing model name> UEFF ([model parameters])
Example
.MODEL JKDLY UEFF (tppcqlhty=10ns tppcqlhmx=25ns tpclkqlhty=12ns +twpclty=15ns tsudclkty=4ns)
Parameter |
Description |
Units |
|
|
|
TWCLKLMN |
Width: min clk/clkb low |
sec |
|
|
|
TWCLKLTY |
Width: typ clk/clkb low |
sec |
|
|
|
TWCLKLMX |
Width: max clk/clkb low |
sec |
|
|
|
TWCLKHMN |
Width: min clk/clkb high |
sec |
|
|
|
TWCLKHTY |
Width: typ clk/clkb high |
sec |
|
|
|
TWCLKHMX |
Width: max clk/clkb high |
sec |
|
|
|
TSUDCLKMN |
Setup: min j/k/d to clk/clkb edge |
sec |
|
|
|
TSUDCLKTY |
Setup: typ j/k/d to clk/clkb edge |
sec |
|
|
|
TSUDCLKMX |
Setup: max j/k/d to clk/clkb edge |
sec |
|
|
|
TSUPCCLKHMN |
Setup: min preb/clrb hi to clk/clkb edge |
sec |
|
|
|
TSUPCCLKHTY |
Setup: typ preb/clrb hi to clk/clkb edge |
sec |
|
|
|
TSUPCCLKHMX |
Setup: max preb/clrb hi to clk/clkb edge |
sec |
|
|
|
THDCLKMN |
Hold: min j/k/d after clk/clkb edge |
sec |
|
|
|
THDCLKTY |
Hold: typ j/k/d after clk/clkb edge |
sec |
|
|
|
THDCLKMX |
Hold: max j/k/d after clk/clkb edge |
sec |
|
|
|
Table 23-8b Edge-triggered flip-flop timing model parameters
The parameter <no. of flip-flops> specifies the number of flip-flops and is available only for SPICE circuits or libraries. Schematic flip-flop components are available only as singles. The three nodes, <presetbar node>, <clearbar node>, and <clock node> are common to all flip-flops in the array.
524 Chapter 23: Digital Devices
J |
K |
CLK |
PREB |
CLRB |
Q |
QB |
|
|
|
|
|
|
|
X |
X |
X |
1 |
0 |
0 |
1 |
|
|
|
|
|
|
|
X |
X |
X |
0 |
1 |
1 |
0 |
|
|
|
|
|
|
|
X |
X |
X |
0 |
0 |
Unstable |
Unstable |
|
|
|
|
|
|
|
X |
X |
0 |
1 |
1 |
Q' |
QB' |
|
|
|
|
|
|
|
X |
X |
1 |
1 |
1 |
Q' |
QB' |
|
|
|
|
|
|
|
0 |
0 |
↓ |
1 |
1 |
Q' |
QB' |
|
|
|
|
|
|
|
0 |
1 |
↓ |
1 |
1 |
0 |
1 |
|
|
|
|
|
|
|
1 |
0 |
↓ |
1 |
1 |
1 |
0 |
|
|
|
|
|
|
|
1 |
1 |
↓ |
1 |
1 |
QB' |
Q' |
|
|
|
|
|
|
|
Table 23-9 JKFF flip-flop truth table
D |
CLK |
PREB |
CLRB |
Q |
QB |
|
|
|
|
|
|
X |
X |
1 |
0 |
0 |
1 |
|
|
|
|
|
|
X |
X |
0 |
1 |
1 |
0 |
|
|
|
|
|
|
X |
X |
0 |
0 |
Unstable |
Unstable |
|
|
|
|
|
|
X |
0 |
1 |
1 |
Q' |
QB' |
|
|
|
|
|
|
X |
1 |
1 |
1 |
Q' |
QB' |
|
|
|
|
|
|
0 |
↑ |
1 |
1 |
0 |
1 |
|
|
|
|
|
|
1 |
↑ |
1 |
1 |
1 |
0 |
|
|
|
|
|
|
Table 23-10 DFF flip-flop truth table
Gated latch
Two types of gated latches are provided, the SRFF and the DLTCH. Both devices change during the high level of the gate.
SPICE format
U<name> SRFF(<no. of latches>)
+<digital power node> <digital ground node> +<presetbar node> <clearbar node> <gate node> +<first s node>...<last s node>
+<first r node>...<last r node> +<first q node>...<last q node> +<first qbar node>...<last qbar node>
+<timing model name> <I/O model name> +[MNTYMXDLY=<delay select value>] +[IO_LEVEL=<interface subckt select value>]
U<name> DLTCH(<no. of latches>) +<digital power node> <digital ground node>
+<presetbar node> <clearbar node> <gate node> +<first d node>...<last d node>
+<first q node>...<last q node> +<first qbar node>...<last qbar node>
+<timing model name> <I/O model name> +[MNTYMXDLY=<delay select value>] +[IO_LEVEL=<interface subckt select value>]
Examples
U1 SRFF(2) $G_DPWR $G_DGND + PREBAR CLRBAR CLK
+S1 S2 R1 R2 Q1 Q2 Q1BAR Q2BAR
+D0_SRFF IO_STD IO_LEVEL=1
U4 DLTCH(1) $G_DPWR $G_DGND +PREB CLRB GATE
+D1 Q QBAR D_DLTCH IO_ALS
526 Chapter 23: Digital Devices
