Micro-Cap v7.1.6 / RM

Special Component editor fields

Inputs <number of inputs> Outputs <number of outputs>

The Component editor has two special fields for PLA devices, 'Inputs' and 'Outputs'. When you enter these values, MC7 places the specified input and output pins on the display and you must drag them into place on the shape.

Definitions

<pld type> selects the type of gate and is chosen from the following list:

FILE = <"file name constant" | |file name expression| >

This attribute denotes the name of a JEDEC format file in one of two formats:

File name constant enclosed in double quotes ("")

File name expression enclosed in double bars (||)

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B Binary data

O Octal data (most significant bit =lowest address)

X Hex data (most significant bit =lowest address)

<program data>$

This text string contains data values that program the PLA. If the data value for a particular input column variable is a '0', the input column is not connected to the gate. If the data value is a '1', the input column is connected to the gate. The phrase "connected" means that a new input to the gate is created and the input (column) line is connected to the new gate input. The data values start at the zero address. For example:

True only(PLAND, PLOR, PLNAND, PLNOR, PLXOR, PLNXOR)

The zero address specifies the first input to the first output gate. The next input specifies the second input to the first output gate, and so on until all possible input connections have been specified. The process repeats for all possible input connections to the second gate until the last gate has been programmed.

True and complement(PLANDC, PLORC, PLNANDC, PLNORC, PLXORC, PLNXORC)

True and complement programming is like true only programming, except that the complement is interleaved and placed after the true. The zero address programs the first true input to the first output gate. The next input programs the connection of the first complement input to the first gate. The next input programs the connection of the second true input to the first output gate. The next input programs the connection of the second complement input to the first gate, and so on until all possible true and complement input connections have been programmed. The process is repeated for all possible true and complement input connections to the second gate until the final gate has been programmed.

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The data values must be delimited by dollar signs ($). They may be separated by spaces or placed on continuation lines.

Model statement form

.MODEL <timing model name> UPLD ([model parameters])

Example

.MODEL PLD1 UPLD (TPLHMN=10ns TPLHTY=25ns TPLHMX=35ns)

Table 23-16 PLA timing model parameters

540 Chapter 23: Digital Devices

Multi-bit A/D converter

SPICE format

U<name> ADC(<bits>)

+<digital power node> <digital ground node> +<in node><ref node> <gnd node> <convert node> +<status node> <over-range node>

+<output msb node> <output lsb node> +<timing model name> <I/O model name> +[MNTYMXDLY=<delay select value>] +[IO_LEVEL=<interface subckt select value>]

Example

U10 ADC(8) $G_DPWR $G_DGND

+analog_in reference 0 convert status over B7 B6 B5 B4 B3 B2 B1 B0 +IO_STD_OC_ST

Schematic format

PART attribute <name>

Example

U10

TIMING MODEL attribute <timing model name>

Example

AF_04

I/O MODEL attribute <I/O model name>

Example

IO_AC

MNTYMXDLY attribute <delay select value>

Example 1

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The ADC device converts the analog voltage difference between the <in node> pin and the <gnd node> pin to an equivalent digital representation. The digital output is the binary equivalent of:

V(in node, gnd node)2<bits>

___________________

V(ref node, gnd node)

If the analog input value, V(in node, gnd node), is less than zero, then all data bits are set to '0', and over-range is set to '1'. If this value exceeds V(ref node, gnd node) then all data bits are set to '1', and the over-range pin is again set to '1'.

The sampling of the input voltage occurs on the rising edge of the CONVERT signal. Only one conversion is performed per rising edge.

The data output pins go to the 'X' state and the STATUS pin goes to the '1' state TPCS seconds after the rising edge of the CONVERT signal. TPSD seconds later, the data output pins change to valid data. TPDS seconds later, the STATUS pin goes to the '0' state. This timing is summarized in the diagram below:

Figure 23-2 ADC timing diagram

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Model statement form

.MODEL <timing model name> UADC ([model parameters])

Example

.MODEL A1 UADC (TPCSMN=5ns TPCSTY=15ns TPCSMX=25ns)

Table 23-17 ADC timing model parameters

See the sample circuit AD16 for an example of the use of this type of device.

544 Chapter 23: Digital Devices

Multi-bit D/A converter

SPICE format

U<name> DAC(<no. of bits>)

+<digital power node> <digital ground node> +<out node> <ref node> <gnd node> +<input msb node> <input lsb node> +<timing model name> <I/O model name> +[MNTYMXDLY=<delay select value>]

+[IO_LEVEL=<interface subckt select value>]

Example

U10 DAC(8) $G_DPWR $G_DGND

+analog_out reference 0 B7 B6 B5 B4 B3 B2 B1 B0 + D0_EFF IO_STD_ST

Schematic format

PART attribute <name>

Example

U10

TIMING MODEL attribute <timing model name>

Example

DACTM

I/O MODEL attribute <I/O model name>

Example

IO_HCT

MNTYMXDLY attribute <delay select value>

Example 1

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