Micro-Cap v7.1.6 / RM

Format definitions

BOOLEAN:

Marks the start of a group of one or more <boolean assignments> used as temporary variables in subsequent <delay assignments>. A <boolean assignment> is one of the following forms:

<boolean variable> = {<boolean expression>} <boolean variable> = any valid variable name

<boolean expression>

This is a C-like, infix-notation expression which generates one of the two boolean states, TRUE or FALSE. The expression must be enclosed in curly braces {...}. The <boolean expression> may use the continuation character (+) to span more than one line. Boolean expression operators and their precedence are as follows:

Table 23-20 Boolean expression operators

Operands are one of the following:

Previously assigned <boolean variables> Reference functions

Transition functions

<boolean constants> (TRUE or FALSE)

Logic levels ,('0, '1, 'R, 'F, 'X) may be used as operands for the '==' and '!=' operators only. This lets the boolean logic examine input states as in, "START={COUNT=='R & RESET=='0}". Note that the mandatory single quote (') is a part of the constant name.

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Transition functions using the Z state should be used only within TRISTATE sections. Open collector transitions should be modeled with the TRN_LH and TRN_HL functions.

PINDLY:

Marks the start of a group of one or more <delay assignments> used to assign path delays to the PINDLY input / output channels. A <delay assignment> is of the following form:

<output node>* = { <delay expression> }

<output node>

One or more of the PINDLY <output node> names mentioned in the list, <first digital output node>...<last digital output node>. Several outputs may share the same rules by including them on the left side separated by spaces or commas.

<delay expression>

An expression which returns a set of three delay values (min,typ,max) for use on the specified output delay channel. There are two forms:

DELAY(<min>,<typ>,<max>)

This form simply specifies the delays directly. For example:

...

+PINDLY: OUT1 , OUT2 = { DELAY(10ns, -1, 20ns) }

...

Note the use of -1 causes the system to calculate the value using the unspecified propagation delay rules.

The second form uses a more complex CASE statement. Its form is:

CASE(<boolean expression_1>,<delay expression_1>, ;rule 1 <boolean expression_2>,<delay expression_2>, ;rule 2

...

<boolean expression_n>,<delay expression_n>, ;rule n <default delay expression> )

The CASE statement is comprised of a set of one or more rules. Each rule has a <boolean expression> and a <delay expression> and is evaluated in the order listed in the CASE statement. The first <boolean expression> that returns TRUE causes the <delay expression> to be assigned to the <output nodes>. If no <delay expression> returns TRUE, the <default delay expression> is assigned to the

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TRISTATE:

Marks the start of a group of one or more tri-state <delay assignments> used to assign path delays to tri-state input / output channels. Unlike a PINDLY, a TRISTATE is controlled by an <enable node>.

Following the TRISTATE: keyword, an <enable node> and its polarity are specified. The polarity is specified by choosing one of two keywords:

The <enable node> controls all <output nodes> in the current TRISTATE section.

The <delay expressions> in a TRISTATE section may employ the Z-state transition functions.

Simulation behavior

The PINDLY statement is evaluated when any input, enable, or output pin changes state. Each <input node> is associated with a corresponding <output node> in the same order of occurrence on the line. The BOOLEAN sections are evaluated first, then the PINDLY and TRISTATE sections are evaluated and the delays for changing <output nodes> calculated. Changing <output nodes> are then scheduled for a state change to the new <input node> state after the appropriate delay.

Example

This example shows a mixture of BOOLEAN, PINDLY, and TRISTATE sections:

U4DLY PINDLY(9,1,13) DPWR DGND

+Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 INTBAR_O

+OE

+STB M S1BAR S2 CLRBAR DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8

+DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 INTBAR

+IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

+

+BOOLEAN:

+DATA = {CHANGED(DI1,0) | CHANGED(DI2,0) |

+CHANGED(DI3,0) | CHANGED(DI4,0) |

+CHANGED(DI5,0) | CHANGED(DI6,0) |

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This attribute is a full CONSTRAINT statement or, more commonly, the name of a CONSTRAINT statement defined with a .define statement in the text area.

Examples

C381_STD ;defined in the text area

WIDTH: NODE = MRBAR MIN_LO = 5n

FREQ: NODE = CP MAXFREQ = 130MEG

I/O MODEL attribute <I/O model name>

Example

IO_STD

IO_LEVEL attribute <interface subckt select value>

Example 0

POWER NODE attribute <digital power node>

Example

$G_DPWR

GROUND NODE attribute <digital ground node>

Example

$G_DGND

Special Component editor pin fields

Inputs <inputs>

The Component editor has a special 'Inputs' field for CONSTRAINTs. You don't edit these fields directly. Instead, you click in the Shape/Pin Display and add an input pin. This lets you define the names and pin locations of the input pins used by the constraint device.

Constraint devices are used mainly for modeling commercial parts, and are found principally in subcircuits in the Digital Library text files. Because they can have a large number of input pins, and since a component in the Component Library re-

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quires the input pin placements, including all possible constraint devices in the library is not feasible. Only a few such devices are to be found in the library, and they are mainly for illustration. These devices are really targeted for use in text file subcircuits. While you can use them directly in schematics, their real power issues from their use in the models of commercial digital parts.

Format definitions

BOOLEAN:

Marks the start of a group of one or more <boolean assignments> used as temporary variables in subsequent <specifications>. A <boolean assignment> is of the following form:

<boolean variable> = {<boolean expression>}

<boolean expression>

This is the same as in the PINDLY, with the singular exception that the transition functions (TRN_pc) are not available.

SETUP_HOLD:

Marks the start of a <setup_hold specification>. The format is as follows:

+SETUP_HOLD:

+CLOCK <assertion edge> = <input node>

+DATA(<no. of data inputs>) = <first input node>...<last input node> +[SETUPTIME=<time value>]

+[HOLDTIME=<time value>] +[WHEN=<boolean expression>] +[MESSAGE="<extra message text>"] +[ERRORLIMIT=<limit value>]

The CLOCK argument <input node> defines the input node that serves as a reference for the setup/hold specification. The CLOCK <assertion edge> is one of the following:

LH This specifies that the clock low to high edge is the assertion edge. HL This specifies that the clock high to low edge is the assertion edge.

The DATA arguments <first input node>...<last input node> specify one or more input nodes whose setup or hold time is to be measured. There must be at least one input node. The arguments must be separated by a space or a comma.

The SETUPTIME argument <time value> specifies the minimum time that all

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DATA <input nodes> must be stable prior to the <assertion edge> of the clock. The <time value> must be positive or zero. If an <input node> has a setup time that depends upon whether the data is LO or HI, then you can use one of these specialized forms:

SETUPTIME_LO=<time value>

This is the setup time for a low data state prior to the clock <assertion edge>.

SETUPTIME_HI=<time value>

This is the setup time for a high data state prior to the clock <assertion edge>.

If either of these setup time specifications is zero, MC7 will skip its check.

The HOLDTIME argument <time value> specifies the minimum time that all DATA <input nodes> must be stable after the <assertion edge> of the clock. The <time value> must be positive or zero. If an <input node> has a hold time that depends upon whether the data is LO or HI, then you can use one of these:

HOLDTIME_LO=<time value>

This is the hold time for a low data state after the clock <assertion edge>.

HOLDTIME_HI=<time value>

This is the hold time for a high data state after the clock <assertion edge>.

How it works

The evaluation begins when the specified Clock node experiences the specified <assertion edge>. The WHEN <boolean expression> is evaluated and if TRUE, all SETUPTIME and HOLDTIME blocks with nonzero values are checked during this clock cycle. If the WHEN evaluates to FALSE, then no checks are done for this clock cycle. The WHEN function disables checking when it is inappropriate, as for example, during a RESET or PRESET operation.

Setup time checks occur at the CLOCK <assertion edge>. If the specified hold time is zero, simultaneous CLOCK and DATA transitions are allowed, but the previous DATA transition is checked for setup time. If the hold time is not zero, simultaneous CLOCK and DATA transitions are reported as errors. Hold time checks are done on any DATA input that changes after the CLOCK <assertion edge>. If the setup time is zero, simultaneous CLOCK and DATA transitions are allowed, but the next DATA transition occurring before the non-asserting edge is checked for hold time. If the setup time is not zero, simultaneous CLOCK and DATA transitions are reported as errors.

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