Micro-Cap v7.1.6 / RM

Table 23-11A Gated latch timing model parameters

Model statement form

.MODEL <timing model name> UGFF ([model parameters])

Example

.MODEL SR1 UGFF (tppcqlhty=10ns tppcqlhmx=25ns tpgqlhty=12ns +twpclty=15ns tsudgty=4ns)

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Table 23-11B Gated latch timing model parameters (continued)

The parameter <no. of latches> specifies the number of latches in the array and is available only for SPICE text circuits or text subckt libraries. Schematic latches are available only as singles. The three nodes, <presetbar node>, <clearbar node>, and <gate node> are common to all latches in the array.

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Table 23-12 SRFF latch truth table

Table 23-13 DLTCH latch truth table

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Pullup and pulldown

These devices provide a constant output level at a user-specified strength. The outputs are as follows:

These devices provide a strong '1' to pull up or a strong '0' to pull down a group of open-collector devices whose outputs are wired together.

SPICE format

U<name> <resistor type>(<number of resistors>) +<digital power node> <digital ground node> +<output node>*

+<I/O model name>

+[IO_LEVEL=<interface subckt select value>]

<resistor type> is one of the following:

<number of resistors> specifies the number of resistors in the array.

Note that these devices are digital devices, not analog devices. Their sole purpose is to provide a strong constant level to a set of open-collector digital devices whose outputs are wired together. Open-collector devices are simply digital devices with a very large value of DRVH in their I/O model.

PULLUP and PULLDN devices do not use timing models since there is no delay associated with them. They do, however, need I/O models, since they are digital devices.

Example

U1 PULLUP(8) +$G_DPWR $G_DGND +A1 A2 A3 A4 A5 A6 A7 A8 + IO_STD

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Schematic format

PART attribute <name>

Example

U1

I/O MODEL attribute <I/O model name>

Example

IO_ALS

IO_LEVEL attribute <interface subckt select value>

Example 1

POWER NODE attribute <digital power node>

Example

$G_DPWR

GROUND NODE attribute <digital ground node>

Example

$G_DGND

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Delay line

This device provides a constant delay according to the timing model parameters. Unlike the other digital devices, there is no inertial cancellation of narrow pulse widths through delay lines.

SPICE format

U<name> DLYLINE

+<digital power node> <digital ground node> +<input node> <output node>

+<timing model name> <I/O model name> +[MNTYMXDLY=<delay select value>] +[IO_LEVEL=<interface subckt select value>]

Example

U1 DLYLINE +$G_DPWR $G_DGND +IN OUT

+ DMOD IO1

Schematic format

PART attribute <name>

Example

U1

TIMING MODEL attribute <timing model name>

Example

DELAY1

I/O MODEL attribute <I/O model name>

Example

IO_STD

MNTYMXDLY attribute <delay select value>

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Programmable logic arrays

The programmable logic array is designed to allow modeling of a wide variety of programmable logic devices. The device is constructed of a user-specified number of inputs, visualized as columns, and a user-specified number of outputs, which form the rows. Each output (row) is a gate, whose inputs are selected from the inputs (columns). The device is programmed by choosing the inputs to be a part of the gate. The type of gate is determined by the PLA type. A PLNAND provides NAND gates, a PLOR provides OR gates, and so on. The PLA device provides a programmable core for modeling commercial PLA parts.

There are two ways to program the PLA. The normal way is to provide the data in a JEDEC format file. These files are normally created as the primary output of a PLA design program. The second method is to include the data directly in the SPICE command line or, for schematics, in the DATA attribute.

SPICE format

U<name> <pld type>(<no. of inputs>,<no. of outputs>) +<digital power node> <digital ground node>

+<input node>* <output node>* +<timing model name> <I/O model name>

+[FILE=<"file name constant" | |file name expression|>] +[DATA=<data constant> | <radix flag>$<program data>$] +[MNTYMXDLY=<delay select value>] +[IO_LEVEL=<interface subckt select value>]

Schematic format

PART attribute <name>

Example

U10

TIMING MODEL attribute <timing model name>

Example

PL_04

I/O MODEL attribute <I/O model name>

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