0
Y[um]
0.5 |
|
|
Electrostatic Potential [V] |
|
|
|
|
1.6E+00 |
|
|
|
|
1.2E+00 |
|
|
|
|
7.8E–01 |
|
|
|
|
3.7E–01 |
1 |
|
|
|
–3.6E–02 |
|
|
|
–4.5E–01 |
–1 |
–0.5 |
0 |
0.5 |
1 |
|
|
X[um] |
|
|
(a)
–0.05 |
|
0 |
|
0.05 |
Electrostatic Potential [V] |
|
|
1.6E+00 |
|
1.2E+00 |
|
7.8E–01 |
0.1 |
3.7E–01 |
|
–3.6E–02 |
|
–4.5E–02 |
–0.1 |
–0.05 |
0 |
0.05 |
0.1 |
|
|
X[um] |
|
|
(b)
COLOR FIGURE 6.6
Electrostatic potential contours in (a) long channel Leff = 1 m and (b) short channel Leff = 65 nm (Vgs = 1.0V,Vds = 0.05V).
Polysilicon gate
STI oxide
Depletion Width Contour
p-sub
Gate oxide (SiO2)
Electrostatic Potential [V] 5.3E–01
3.4E–01
1.4E–01
–5.5E–02
–2.5E–01
–4.5E–01
–0.0.5 |
0 |
0.05 |
0.1 |
0.15 |
|
|
Width (um) |
|
|
COLOR FIGURE 6.17
Cross-section along the width of a trench-isolated MOSFET.
|
|
|
|
Front gate |
|
|
|
0 |
|
|
|
|
Front oxide |
|
|
|
|
|
|
Y[um] |
0.02 |
Source |
|
|
|
Drain |
|
0.04 |
|
|
|
|
Back oxide |
|
|
|
|
|
|
|
|
|
|
Back gate |
|
|
|
|
–0.04 |
–0.02 |
0 |
0.02 |
0.04 |
|
|
|
|
X[um] |
|
|
COLOR FIGURE 6.26
A typical DG-MOSFET structure as simulated in TCAD.
–2.50
2.50
7.50
0.00 |
1.00 |
2.00 |
3.00 |
4.00 |
5.00 |
|
|
Distance (microns) |
|
|
COLOR FIGURE 8.2
Deposition of negative photoresist of thickness 1 μm on grown oxide; a portion (2 to 3 μm) of the photoresist is being etched out by using mask NBL.
0.00
2.00
4.00
0.00 |
1.00 |
2.00 |
3.00 |
4.00 |
5.00 |
Distance (microns)
COLOR FIGURE 8.3
Implantation of antimony of pearson tilt = 7, dose = 1.0 e15, and energy = 100, which will be used as NBL.
0.00
4.00
8.00
0.00 |
1.00 |
2.00 |
3.00 |
4.00 |
5.00 |
Distance (microns)
COLOR FIGURE 8.4
Placement of antimony dopant in the wafer after the application of drive-in voltage on it.
–15.00
–5.00
5.00
0.00 |
1.00 |
2.00 |
3.00 |
4.00 |
5.00 |
Distance (microns)
COLOR FIGURE 8.5
Placement of NBL and epitaxial growth on the initial wafer.
–13.50
–13.00
–12.50
–12.00 |
1.00 |
2.00 |
3.00 |
4.00 |
5.00 |
0.00 |
Distance (microns)
COLOR FIGURE 8.6
Pad oxide on the wafer is shown; here the y-axis has been chosen up to −12 μm.
–13.50
–13.00
–12.50
–12.00 |
1.00 |
2.00 |
3.00 |
4.00 |
5.00 |
0.00 |
Distance (microns)
COLOR FIGURE 8.7
Structure of the wafer after formation of the gate oxide.
|
–14.00 |
|
|
|
|
–13.50 |
|
|
|
(microns) |
–13.00 |
|
|
|
Distance |
|
|
|
|
|
|
|
|
–12.50 |
|
|
|
|
–12.00 |
1.00 |
2.00 |
3.00 |
|
0.00 |
Distance (microns)
COLOR FIGURE 8.8
Polysilicon material deposition on the grown gate oxide material.
|
–14.00 |
|
|
|
|
–13.50 |
|
|
|
(microns) |
–13.00 |
|
|
|
Distance |
|
|
|
|
|
|
|
|
–12.50 |
|
|
|
|
–12.00 |
1.00 |
2.00 |
3.00 |
|
0.00 |
Distance (microns)
COLOR FIGURE 8.9
Polysilicon gate formation on the gate oxide after selective polysilicon material by etching from the wafer; polysilicon gate length is 2.5 μm.
–14.00
–13.50
–13.00
–12.50
–12.00 |
1.00 |
2.00 |
3.00 |
4.00 |
5.00 |
0.00 |
Distance (microns)
COLOR FIGURE 8.12
The structure achieved by executions of etch photoresist and etch nitride all statements.
–15.00
–13.00
–11.00
0.00 |
1.00 |
2.00 |
3.00 |
4.00 |
5.00 |
Distance (microns)
COLOR FIGURE 8.13
Borophosphosilicate glass deposition before the first layer of metal contact to the device.
–14.00
–13.50
–13.00
–12.50
–12.00 |
1.00 |
2.00 |
3.00 |
4.00 |
5.00 |
0.00 |
Distance (microns)
COLOR FIGURE 8.16
Selective etching has been performed to deposit aluminum through it for the first layer of metal contacts.
|
–14.50 |
|
|
|
|
|
(microns) |
–14.00 |
|
|
|
|
|
–13.50 |
|
|
|
|
|
Distance |
|
|
|
|
|
–13.00 |
|
|
|
|
|
|
|
|
|
|
|
|
–12.50 |
|
|
|
|
|
|
–12.00 |
1.00 |
2.00 |
3.00 |
4.00 |
5.00 |
|
0.00 |
Distance (microns)
COLOR FIGURE 8.17
First layer of metal deposition through the opening of BPSG for the direct contacts from the device.
