Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

Добавил:

Upload Опубликованный материал нарушает ваши авторские права? Сообщите нам.

Вуз:

Новосибирский государственный технический университет

Предмет:

[НЕСОРТИРОВАННОЕ]

Файл:

Vgs = 0.8 V

Vgs = 0.6 V

Vgs = 0.4 V

Vgs = 0.2 V

.pdf

Скачиваний:

187

Добавлен:

11.03.2016

Размер:

34.78 Mб

Скачать

☆

<<< < Предыдущая 16 17 18 19 20 21 22 23 24 25 26 2728 / 4528 29 30 31 32 33 34 35 36 37 38 39 40 > Следующая >>>

Study of Deep Sub-Micron VLSI MOSFETs through TCAD

253

	0.0008
	0.0007
(A/um)	0.0006
(A/um)	0.0005
ds
I
Current,	0.0004
	0.0004
Drain	0.0003
Drain	0.0002
	0.0002
	0.0001
	0	0

FIGURE 6.14

Vgs = 1.1 V

Drain-to-source Voltage, Vds (V)

Drain characteristics of a 65 nm MOSFET.

	16000
Rout(ohm/um)	14000
Rout(ohm/um)	10000						Vgs = 1.1 V
	12000
Resistance,	6000						Vgs = 0.8 V
Resistance,	6000						Vgs = 0.4 V
	8000						Vgs = 0.4 V
Output	8000
Output	4000
	4000
	2000
	0	0.2	0.4	0.6	0.8	1	1.2	1.4
			Drain-to-source Voltage, Vds (V)

FIGURE 6.15

Output resistance versus drain voltage (Leff = 65 nm).

254	Technology Computer Aided Design: Simulation for VLSI MOSFET

6.7 Inverse Narrow Width Effects (INWEs)

As the device dimension is reduced along its width, we come across effects known as the narrow width effects. In LOCOS isolated devices, threshold voltage increases with a decrease in the width of the device. The deep submicron devices isolated using the shallow trench isolation (STI) process are associated with a decrease in the threshold voltage with a reduction in the channel width. This effect associated with the STI MOSFETs is known as the inverse narrow width effect (INWE) [5]. Narrowing the channel width of a transistor affects its performance to an extent comparable to the effects caused by shortening the channel length [9,10]. Hence the study of MOS transistor performances along the width dimension becomes important for the design of low power complementary metal-oxide-semiconductor (CMOS) circuits and memory cells [11,12].

The INWE is primarily caused due to two reasons. First is the combined effect of gate fringing fields through trench oxide and dopant redistribution phenomenon [13,14]. Second is the effect of STI stress [15]. The effect of the latter is dominant for comparatively larger widths, while the former is dominant for narrower widths [15]. STIMOS transistors with channel widths below 1 µm exhibit threshold voltage roll-off where the INWE effect is the dominant cause.

6.7.1 Gate Fringing Field Effect

Figure 6.16 shows the schematic of the cross-section along the width of the STIMOS device. The field lines originating from the gate terminate on charges under the gate through the thin gate oxide. Some of the field lines also terminate on charges along the trench oxide sidewalls. These are the fringing field lines.

Figure 6.17 shows the cross-section along the width of a typical STIMOS device as obtained by using the appropriate slicing tool of ‘Tecplot SV’. The electrostatic potential contours are shown in the figure. It is seen in the figure that the depletion depth (the white contour is the depletion contour) is nonuniform and varies along the width of the device. In wide MOS devices, the enhanced depletion region near the sidewalls caused due to the gate fringing field is a small percentage of the total depletion volume and can be neglected. The depletion depth may then be considered to be uniform throughout the width without resulting in too much of an error in the analysis of the device performances. For devices with small widths, the depletion volume near the sidewalls becomes a large percentage of the total depletion volume. This is referred to as the gate fringing field effect and is illustrated in Figure 6.18.

MOS devices with varying channel widths are created using the Sentaurus Structure Editor and are then simulated using the tool ‘Sentaurus device’. The simulated devices are then visualized using the tool ‘Tecplot SV’. The depletion depths along the width are noted and then plotted as in Figure 6.18.

Study of Deep Sub-Micron VLSI MOSFETs through TCAD

255

Gate

Poly gate

Normal ﬁeld lines through

gate oxide (SiO2)

Width, W

Fringing ﬁeld lines through trench oxide (SiO2)

Depletion region contour

p-substrate

FIGURE 6.16

Cross-section along the width of a trench-isolated MOSFET including gate fringing fields.

It is observed from Figure 6.18 that as the device becomes narrower, the gate fringing increases.

The effect of gate fringing is modeled by a parasitic fringe capacitance. The higher depletion depths at the trench oxide sidewalls are associated with a higher surface potential. Figure 6.19 shows the schematic representation of

Depth (um)

0.05

–0.05

–0.1

	Polysilicon gate	STI oxide
		STI oxide
Depletion Width Contour
	p-sub
–0.0.5	0	0.05

Width (um)

Gate oxide (SiO2)

Electrostatic Potential [V] 5.3E–01

3.4E–01

1.4E–01

–5.5E–02

–2.5E–01

–4.5E–01

0.10.15

FIGURE 6.17 (See color insert)

Cross-section along the width of a trench-isolated MOSFET.

256	Technology Computer Aided Design: Simulation for VLSI MOSFET

Depletion Depth (um)

–0.014
–0.016	W1	= 40 nm
–0.016	W2	= 200 nm
	W3	= 400 nm
–0.018	W4	= 2000 nm
–0.02

–0.022

–0.024

–0.026

–0.028

–1

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

Width (normalized)

FIGURE 6.18

Gate fringing field effect for STI MOSFETs.

the variation of the depletion depth and the corresponding surface potential along the width of the device.

In Figure 6.19(a) the depletion depth at the trench-oxide sidewall is dw max , decreases to a value dw, remains constant at dw beyond a critical point zb, and then finally increases again to dw max at the other sidewall. Figure 6.19(b) shows the variation of the surface potential ψS along the width of the device. ψSM is the surface potential in the middle of the device; ψST is the surface potential at the trench oxide sidewall edges.

Figure 6.20 shows the surface potential profile along the width of a typical simulated device. The gate fringing field through the trench oxide causes the surface potential at the sidewall edges to increase in comparison to that at the middle of the channel width.

The sidewall surface potential ψST varies with Vgs in a similar fashion as the surface potential at the middle ψSM does with Vgs. A typical device has been simulated for different gate biases, and the results are as shown in Figure 6.21.

The surface potential at the center of the device is related to that at the

trench-oxide sidewalls by the relation [13,16]
ψST = lψSM + d	(6.7)

where l is close to unity, and d is a numerical constant expressed as d = nkTq

Study of Deep Sub-Micron VLSI MOSFETs through TCAD

257

Depletion depth

0	zb Channel width	W
0		z
dw
dwmax

Surface potential

ΨST

ΨSM

x	0 Channel width	W	z
		W
(a)	(b)

FIGURE 6.19

(a) Variation of depletion depth along the channel width. (b) Variation of surface potential along the channel width.

where kTq is the volt equivalent of temperature. The value of n lies between 1.2 and 2.3 for devices with largely varying dimensions like 200 nm gate length to 40 nm gate length having substrate doping ranging from 1017/cc to 1019/cc.

6.7.2 Dopant Redistribution

The depletion charge density does not remain constant along the entire width of the channel. This is due to the non-uniformity of the doping concentration

Electrostatic Potential (V)

0.45

0.4

0.35

–0.06	–0.04	–0.02	0	0.02	0.04	0.06
			Width (um)

FIGURE 6.20

Plot of surface potential against the width of the device.

258	Technology Computer Aided Design: Simulation for VLSI MOSFET

1.5

ΨSM ΨST

Ψs (V)

0.5

0 0	0.2	0.4	0.6	0.8	1	1.2	1.4	1.6	1.8	2
			Gate-to-source Voltage, Vgs (V)

FIGURE 6.21

Simulation results showing variation of ψST and ψSM with Vgs (Vsb = 0V).

along the width of the channel which is caused by dopant redistribution (comprised of dopant segregation [17–19] and transient-enhanced diffusion, TED [20]). After the gate oxidation processing step, dopant atoms in the active channel regions of the transistors start to diffuse out to the adjacent trench oxide/Si interface. This is referred to as the dopant segregation effect [21]. In particular, boron in NMOS transistors gets depleted at the STI edges and segregates to the oxide/Si interface [17]. Boron segregation reduces the B-concentration near the STI edges. If the active area of the device is narrow enough, boron segregation would reduce the boron concentration significantly even at the center of the channel [19]. Further, during the silicon processing step, ion implantation of the dopant impurities dislodges silicon atoms from their lattice sites, which are known as interstitial silicon atoms. A subsequent annealing step repairs some of these lattice damages. The remaining interstitial silicon atoms play an active role in the diffusion of the dopant impurities. High concentrations of these silicon atoms enhance boron diffusion. This phenomenon is known as transient-enhanced diffusion (TED). The TED process leads to a substantial decrease of the boron concentration in proximity to the STI edge relative to the center of the channel [20]. Again if the device is narrow enough, the decrease in the boron concentration may take place significantly even at the center of the channel. The doping profile along the channel width is expressed as [22]

	Na − Nt		z + W			2	z − W			2
N (z) =		erf					− erf				+ Nt	(6.8)
				2	Dt			2	Dt
	2

Study of Deep Sub-Micron VLSI MOSFETs through TCAD

259

Peak Doping Concentration, Nc (/cu.cm)

× 1018

3.4

3.2

2.8

2.6

2.4

2.2

0	0.2	0.4	0.6	0.8	1	1.2	1.4	1.6	1.8	2
				Width, W (micron)

FIGURE 6.22

Variation of the peak channel doping concentration with the channel width.

where Nt is the doping concentration at the trench oxide sidewalls, Na is the substrate doping concentration, and 2 Dt is the diffusion length.

Figure 6.22 shows the plot of the peak concentration against channel width. The figure shows that for large widths, the doping concentration of the channel is equal to Na. However, as the width decreases, the peak concentration in the channel is reduced due to dopant redistribution.

Figure 6.23 shows the plot of the INWE on the threshold voltage of bulk STI MOSFETs with Leff = 40 nm. Different devices with varying channel widths are created using Sentaurus Structure Editor. The source and drain regions are doped with arsenic. A Gaussian doping profile is considered with a peak concentration of 1 × 1019 cm–3. The peak concentration, peak position, and concentration value at the junction depth are specified to the simulator. The channel is doped with boron with a maximum concentration of 3 × 1018 cm–3. An analytical doping profile, identical to that described by Equation (6.8) has been defined to incorporate the phenomenon of dopant redistribution. The specified parameters are maximum concentration and inflection point. The constructed structure is subsequently meshed and simulated using the respective tools. The meshing strategy ensures that fine elements are generated for the critical parts of the device (active region) and coarse elements for the bulk regions.

6.8 Advanced Device Structures

Scaling of MOSFETs has led to several serious limitations; for example,

(1) device performance compromised due to undesirable effects such as threshold voltage roll-off, drain-induced barrier lowering (DIBL), degraded

260	Technology Computer Aided Design: Simulation for VLSI MOSFET

reshold Voltage Change, VthINWE (mV)

0
–20
–40
–60
–80
–80								Vsb = 0 V
								Vsb = 0.5 V
–1000.1	0.2	0.3	0.4	0.5	0.6	0.7	0.8	0.9	1
				Width, W (log scale)

FIGURE 6.23

Inverse narrow width effect (INWE) on the threshold voltage versus channel width (Vgs = 1.0V, Vds = 0.05 V, Vsb = 0.5 V).

subthreshold slope; (2) technological barriers like the manufacturing of optical equipment required for the reduction in the wavelength of light for lithography procedures; (3) gate-oxide thickness reduction leading to quantum mechanical tunneling, which in turn necessitates the introduction of gate dielectric materials with high dielectric constants so that the physical thickness of the dielectric can be increased; and (4) high doping between the source and drain which increases the parasitic capacitance between the source, drain, and the substrate.

All of the above led to the development of the silicon-on-insulator (SOI) technology.

6.8.1 SOI Structures

SOI structures are of two types. These are partially depleted SOI (PDSOI) and fully depleted SOI (FDSOI). In PDSOI, the silicon film is larger than the sum of the gate depletion widths from the front and back ends. These devices exhibit a floating body effect (kink effect). This occurs when carriers of the same type as the body, generated by impact ionization near the drain, are stored in the floating body. This alters the body potential and hence the threshold voltage. A way to minimize this is to use body contacts. However, the body effect advantage is lost in that case. In FDSOI, the silicon film is thin enough that the entire film is depleted before the threshold condition is attained. These devices exhibit a steeper subthreshold slope as compared to the bulk devices. The FDSOI devices were found to perform better than the PDSOI.

Study of Deep Sub-Micron VLSI MOSFETs through TCAD

261

Gate

Source

Drain

Buried oxide (BOX)

Silicon substrate (Back gate)

FIGURE 6.24

Conventional thin film SOI MOSFET.

Figure 6.24 shows the schematic of a conventional thin film SOI MOSFET structure. Most of the electric field lines as shown in Figure 6.24 from the source and drain propagate through the buried oxide (BOX) layer before reaching the channel layer. The SOI structures exhibited lower leakage, low junction capacitance, low latch-up, and better subthreshold swing [23–25]. The performance of these devices in regard to SCEs depends on the silicon film thickness, BOX layer thickness, and doping concentrations [26].

In the deep sub-micron regime, the merits offered by the FDSOI devices diminished, and then double gate structures were found to be more promising.

6.8.2 Double Gate (DG) MOSFETs

The DG-MOSFETs are very attractive to improve the performance of CMOS devices and to overcome some of the difficulties faced in the downscaling of MOSFETs into the deep sub-micron regime. Threshold voltage roll-off, DIBL, off-state leakage, etc., are significantly reduced; hence, these devices are preferred in nanoscale circuits [27–29].

Figure 6.25 shows the schematic diagram of a typical DG-MOSFET. It consists of a silicon slab sandwiched between two oxide layers. A metal or a polysilicon film contacts the two oxide layers [26]. These act as the front and back gate electrodes that create inversion layers near the two Si-SiO2 interfaces

Gate

Source

Drain

Gate

FIGURE 6.25

A typical DG-MOSFET.

262 Technology Computer Aided Design: Simulation for VLSI MOSFET

upon the application of a suitable bias. Thus there are two MOSFETs that share the same source, drain, and substrate.

The salient features of a DG-MOSFET are control of the SCEs by device geometry and not by doping (channel doping or halo doping) as done in bulk MOSFETs. The two gate electrodes jointly control the carriers, thereby screening the effect of drain field from the channel. Additionally, the thin silicon channel leads to a stronger coupling of the gate potential with the channel potential. The reduced SCEs lead to greater scalability than bulk MOSFETs. The undoped body (intrinsic channel) reduces mobility degradation by eliminating impurity scattering, thereby improving the carrier transport. The random microscopic dopant fluctuations are also avoided [30]. The current drive (or gate capacitance) per unit area is increased [31].

The DG-MOSFETs are again of two types, symmetric DG-MOS and asymmetric DG-MOS [23]. In the former, the two oxide thicknesses are the same, the two gates have the same flat-band voltage, and the gates are connected together. In the latter, the two oxide thicknesses are different.

Figure 6.26 shows the cross-section along the length of a DG-MOSFET

structure as seen in the tool ‘Tecplot SV’ of TCAD.
Figure 6.27 shows	the	subthreshold	characteristics of	the simu-
lated DG-MOSFET for	two	drain biases.	The lower curve	corresponds

to Vds = 0.05 V, and the upper one corresponds to Vds = 0.5 V. The subthreshold swing for Vds = 0.05 V is calculated to be 75 mV/decade, and that for Vds = 0.5 V is 80 mV/decade.

Y[um]

			Front gate
0					Front oxide
0
0.02	Source				Drain
0.04					Back oxide
					Back oxide
			Back gate
	–0.04	–0.02	0	0.02	0.04
			X[um]

FIGURE 6.26 (See color insert)

A typical DG-MOSFET structure as simulated in TCAD.

<<< < Предыдущая 16 17 18 19 20 21 22 23 24 25 26 2728 / 4528 29 30 31 32 33 34 35 36 37 38 39 40 > Следующая >>>