Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

0

Y[um]

(a)

–0.1 –0.05 0 0.05 0.1 X[um]

(b)

FIGURE 6.6 (See color insert)

Electrostatic potential contours in (a) long channel Leff = 1 m and (b) short channel Leff = 65 nm (Vgs = 1.0V,Vds = 0.05V).

density, and Cox is the gate oxide capacitance per unit area. Thus, as Qd decreases, Vth also decreases.

The two-dimensional field pattern in a short channel device is due to the close proximity of the source and drain regions. In a short channel device,

the source-drain distance is comparable to the depletion width in the vertical direction [6]. The source-drain potential exerts a strong influence on the gate potential over a significant portion of the channel length. According to the charge sharing model [5,6], when the drain bias is low, all of the depletion charges beneath the gate are not imaged on the gate charges. Rather, some of them are the terminating centers of the field lines originating near the source and drain junctions. Thus there is an effective reduction in the depletion charge density that ultimately leads to the threshold voltage roll-off. This is in contrast to the long channel devices where almost all of the depletion charges are imaged on all the gate charges.

The threshold voltage roll-off as obtained from the TCAD simulator is shown in Figure 6.7. Different devices of varying effective lengths are simulated. The threshold voltages of the different devices are then determined using the tool ‘Inspect’ by the constant current (CC) technique [7]. The reference current is taken to be 10–6 A/µm. It is seen that for long channel lengths the threshold voltage remains almost constant. However, as the channel length is decreased the threshold voltage falls from its long-channel value. This is due to the gradual reduction of the gate control over the channel in the shorter devices. The drain field starts to exert its influence over the gate field in the shorter devices.

The simple assumptions of the charge sharing model, however, render it invalid for high drain and substrate biases. It is therefore unable to explain the drain-induced barrier lowering (DIBL) that is discussed next.

FIGURE 6.7

Threshold voltage roll-off for two different substrate biases (Vgs = 1.0 V,Vds = 0.05 V).

barrier, Vbi of the source-substrate junction. As the drain bias is increased (Vds = 0.5V), the surface potential at the drain end rises to (Vbi + Vds ). Thus the surface potential at the drain end rises by 0.45 V (0.50–0.05 V). Keep in mind that the surface potential values in TCAD are measured relative to a reference. The absolute values are to be calculated accordingly. The DIBL effect for the 65 nm MOSFET as obtained from the simulation results is shown in Figure 6.9. The DIBL coefficient obtained is –0.18.

The threshold voltage roll-off and DIBL can be minimized in three ways:

(1) reduction of the oxide thickness to achieve better gate control over the channel, (2) reduction of the depletion width, and (3) reduction of the sourcedrain junction depth. The depletion width is reduced by increasing the doping concentration in the channel. The source-drain junction depth is effectively reduced by introducing the source-drain extension structure.

Figure 6.10 shows the DIBL effect as obtained from the simulation results

of a MOSFET with a lower SDE depth. Leff = 65 nm, xj = 25 nm,tox = 2.2 nm, and power supply VDD = 1.2V. The threshold voltages are calculated using

the constant current technique. The DIBL coefficient in this case is calculated to be –0.11.

Figure 6.11 shows the subthreshold characteristics of the 65 nm MOSFET as obtained from TCAD simulation results. It shows plots of the drain current (in log scale) against the gate voltage for two different drain voltages. It is seen that with the increase in the drain bias, the subthreshold current increases. For very short devices, the subthreshold slope degrades because the surface potential is controlled more by the drain than the gate. Eventually, the gate loses all its control, and punch-through takes place when a high

FIGURE 6.9

The DIBL effect, Leff = 65nm, xj = 40nm, tox = 3 nm.

FIGURE 6.10

The DIBL effect, Leff = 65 nm, xj = 25 nm, tox = 2.2 nm.

FIGURE 6.11

Subthreshold characteristics for two different drain biases (Leff = 65 nm).

FIGURE 6.12

Transconductance versus Gate-to-source Voltage; (top)Vds = 0.05V and (bottom) Vds = 1.0V.

The drain current, Ids may be written as

or Equation (6.4) may be written as

Therefore, when Vds is low, it is due to Rds , that Ids drops from its value, Ids Rds =0. Thus the maximum value of the transconductance is lowered at low drain bias.

6.6  Drain Characteristics

A significant effect that critically affects the I-V characteristics of a deep submicron MOS transistor is velocity saturation.

6.6.1  Velocity Saturation

In a short channel device, the saturation of the drain current may take place at a much lower Vds value than the Vds value of the longer device. This limits the saturation current of the device. This is illustrated in Figure 6.13 where two curves are drawn: the upper one is for the long channel, and the lower one corresponds to the shorter device. It is seen that the shorter device experiences an early saturation (i.e., the current saturates at a lower drain voltage). This occurs due to velocity saturation and is explained as follows. In the presence of velocity saturation,

where ξsat is the critical electric field beyond which the velocity saturates, and m is the bulk charge factor [8]. Equation (6.6) shows that the short chan-

nel Vdssat is an average of ξsatLeff and long channel Vdssat(= VGS−Vth ). Thus short

m

channel Vdssat is smaller than long channel Vdssat. Hence the drain current for the shorter MOS transistor saturates earlier compared to the long channel value.

FIGURE 6.13

Drain current versus drain-to-source voltage (Vgs = 1.1 V).

6.6.2  Output Resistance

Figure 6.14 shows the simulated drain characteristics of a 65 nm MOSFET. As seen in Figure 6.14, for the short channel MOSFET, the drain current increases beyond saturation. There are two reasons for this. First, due to the increase of drain voltage, threshold voltage falls and hence the current increases. This is the DIBL effect. Second, as Vds is increased beyond the saturation voltage, the saturation point (the point along the channel length where carriers attain the saturation velocity) where the surface channel collapses moves slightly toward the source [6]. That is, the conducting channel length deceases. As a result, the current increases beyond the saturation point. This is the channel length modulation effect.

The increase in the current beyond the saturation point implies that the output conductance is finite. A plot of the output resistance against the drain-to-source voltage is shown in Figure 6.15. It is seen from the curves that in the subthreshold region, the drain current is low so that the output resistance is high. In the strong inversion region, the drain current is high so that output resistance is low. In weak inversion, with the increase of drain bias, the drain current increases due to various second-order effects such as channel length modulation, DIBL effect, etc. Thus the output resistance value falls. However, in strong inversion, the increase of drain current with the increase of drain bias due to the above effects is somewhat counterbalanced by the carrier mobility degradation effect due to the applied gate bias. Therefore the overall increase of drain current is small. Hence the output resistance remains nearly constant.