Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

FIGURE 2.60

Distribution of the gate-channel capacitance as a function of VGS and VDS. (a) CGC as a function of VGS when VDS = 0. (b) CGC as a function of degree of saturation.

function of VGS for VDS = 0. For VGS = 0, the transistor is off as no channel is present, and the total capacitance, equal to WLCox, appears between the gate and the body. When VGS is increased, a depletion region is formed under the gate. This causes the thickness of the gate dielectric to increase, which means a reduction in capacitance. Once the transistor turns on (VGS = Vth), a channel

is formed and CGCB drops off to 0. With VDS = 0, the device operates in the resistive mode and the capacitance divides equally between the source and

the drain, or CGCS = CGCD = WLCox/2. A designer must avoid operation in this region.

When the transistor is on, the distribution of its gate capacitance depends on the degree of saturation, measured by VDS/(VGS – Vth). As in Figure 2.60(b), CGCD gradually drops to 0 for increasing levels of saturation, while CGCS increases to 2/3 COXWL. This also means that the total gate capacitance decreases with an increased level of saturation.

Gate

CGS CGD

CSB

CDB

Bulk

FIGURE 2.62

Different capacitances in MOSFET.

2.23.4  Different MOS Capacitors Together

All the above contributions can be combined in a single capacitive model for the MOS transistor, shown in Figure 2.62. Its components are identified based on the preceding discussions.

2.23.5  Summary of MOS Capacitances

The structure of a MOS transistor is that of a parallel-plate capacitor. The oxide layer acts as an insulator between the two conducting plates: the gate (in polysilicon or metal) and the substrate. The parallel-plate capacitance per unit area is given as

where εr = 3.9 is the dielectric constant of the oxide, ε0 = 8.85 × 1014 F/cm2 is the free-space permittivity, and tox is the oxide thickness. The value of COX remains relatively constant but decreases slightly with increase in substrate

voltage. For semiconductors, the capacitance values are very small and are expressed in units of picofarad (10–12 farad, denoted by pF) or femtofarad (10–15 farad, denoted fF). Similar parallel-plate capacitances are also formed if any overlap regions exist between the gate and the source or the gate and the drain. Even for self-aligned process, a certain amount of channel capacitance between the gate-to-source and the gate-to-drain will exist. These capacitances are denoted CGSO and CGDO, respectively, and must be added with COX to find the total gate capacitance CG of the MOS transistor because they are all connected in parallel. The values of these capacitances are specified by the manufacturer with gate voltage VG, negative or zero—that is, with no depletion region underneath the gate. With an increase in the gate voltage the phenomena of accumulation, depletion, and inversion start to take place. A depletion capacitance CD, formed between the gate and the depletion region boundary, connected in series with COX lowers the effective gate capacitance CG. This is shown in Figure 2.63. The value of CD depends on the depth of the depletion region. The initial depth of the depletion region depends on the built-in contact or barrier potential (typical value 0.7 V) and then increases with increasing VGS. As VGS is increased so as to exceed the threshold voltage Vth, inversion takes place and the channel forms the conducting plate instead of the substrate, the depletion capacitances no longer exist, and the total capacitance shows a marked increase compared to its original oxide capacitance value.

Here we have assumed that the gate voltage is static or varies very slowly so that the phenomena of accumulation, depletion, and inversion take place in proper sequence. If V varies very rapidly (i.e., when the signal frequency of the gate voltage is rather high), the channel may not be formed. On average the device will appear to be in the depleted state all the time, bringing in the effects of the depletion capacitances CD to reduce the total capacitance (Figure 2.63). This dynamic behavior of the capacitance does not really concern us because we will have to operate at considerably lower frequency to guarantee proper switching of each transistor.

It is seen that one part of the capacitances CGS and CGD is due to the gate overlaps at the source and the drain sides. Even if there is no overlap, it is

Gate capacitance

FIGURE 2.63

Variation of the gate capacitance with gate voltage.

useful to visualize CG as consisting of a parallel connection of CGCS and CGCD because the channel can be viewed as a physical extension of the source and the drain regions. When the transistor is operating in the linear region, the two component capacitances have almost equal value; that is, CGCS = CGCD = 0.5 CGC = 0.5 COXWL. When the transistor is saturated, the channel disappears near the drain end and we can assume that CGCS = CGC = 2/3 COXWL.

2.23.6  Interconnect Capacitances

The so-called stray or wiring capacitances of the paths connecting the active channels could become significantly high, depending on the length of the wire, accounting for a major part of the circuit delays. This is because the wiring capacitances need to be charged up together with the gate capacitances for signals to be detected by the transistors. It is therefore convenient to be able to express the wiring capacitances in terms of the gate capacitance of a transistor of some standard size. It is also important to recognize that the diffusion wires are buried in the substrate, and their capacitance depends on two factors: the total area and the perimeter of the wire. The perimeter determines the so-called “side-wall” capacitance, which is at least 20% of the capacitance determined by the total area.

The relevant capacitances are denoted as

CG: gate capacitance (pF/μm2)

Cpln: p-channel source—drain capacitance

Cnln: n-channel source—drain capacitance

Cmf: metal-to-field oxide capacitance

Cmp: metal-to-polysilicon capacitance

Cmt: metal-to-oxide capacitance

Cpf: polysilicon-to-field oxide capacitance

2.24  Moore’s Law

Since the invention of the first calculation machines, miniaturization has been a constant challenge to increase speed and complexity in the microelectronics industry. Linear scaling of device dimensions to a quasi-nanometer level allows building a complex system integrated on a chip which reduces the volume and power consumption per function, while increasing speed [42–45].

The steady downscaling of transistor dimensions over the past two decades has been the main stimulus to the growth of silicon integrated circuits (ICs) and the information industry. Moore’s law [42], which states that the number of

transistors on a given chip can be doubled every two years, has been the guiding principle of the continuous reduction of CMOS device dimension since Gordon Moore, co-founder of Intel, first predicted it in 1965. Over the last few decades, CMOS devices have been scaled down to the sub-100-nm regime. Although the basic device geometry has remained relatively unchanged, the gate length has been reduced from 10 mm in the 1970s to less than 0.1 μm in 2001, and the gate oxide thickness from 1000 Å to less than 20 Å [43].

2.25  Introduction to Scaling

MOS transistors are scaled primarily due to the two reasons mentioned below:

1.Increased device packing density: The design of high-density chips in MOS VLSI technology requires that the packing density of MOSFETs be as high as possible, such that the sizes of the transistors are as small as possible.

2.Improved frequency response (transit time) is proportional to 1/L: If the length of the device is small, then the transit time required for the charged carrier to move from the source to the drain end is small, and thus the device can be operated at higher frequencies.

Two types of scaling are common:

•Constant field scaling

•Constant voltage scaling

Constant field scaling warrants a reduction in the power supply voltage as the minimum feature size is decreased, but it yields the largest reduction in the power-delay product of a single transistor. In contrast, power supply voltage is not reduced in the constant voltage scaling and is therefore the preferred scaling method because it provides voltage compatibility with older circuit technologies. The disadvantage of the constant voltage scaling is that the electric field increases as the minimum feature length is reduced. This leads to velocity saturation, mobility degradation, increased leakage currents, and lower breakdown voltages.

2.26  Constant Field Scaling

The principle of constant field scaling is that the device dimension and the device voltages are to be scaled in such a way that both the horizontal and vertical electric fields remain essentially constant [46]. To ensure the reliability of the device, the electric field in the scaled device must not increase. This

and interconnects) are decreased, the available active current per device is higher, and consequently, the same performance can be achieved with a lower supply voltage. Moving to a new technology generation, however, induces a scale down of the power supply voltage (Vdd), the threshold voltage (Vth), and the gate oxide thickness (TOX). Starting from the 0.18 μm technologies, it appeared that building a transistor with a good active current (Ion) and a low leakage current (Ioff) was becoming more difficult. The four main causes of limitations are as follows:

1.Voltage limits and subthreshold leakage

2.Tunneling currents

3.Statistical dispersions

4.Poly depletion and quantum effects

Two families of transistors were introduced: high-speed transistors and lowleakage transistors. The threshold voltages of the two families are tuned differently, using different channel doping. When moving to more advanced technologies, those two families are no longer sufficient regarding technological constraints. The ITRS introduces three main groups of transistors:

1.High performance (HP)

2.Low operating power (LOP)

3.Low standby power (LSTP)

A new kind of MOS device has been introduced in deep submicron technologies, starting from the 0.18 µm CMOS process generation. The new MOS, called a low leakage MOS device, is available as well as the original, called high-speed MOS.

For I/Os operating at high voltage, specific MOS devices called high voltage MOS are used. The high voltage MOS is built using a thick oxide, two to three times thicker than the low voltage MOS, for handling high voltages, as required by the I/O interfaces, shown in Figure 2.65(a),(b), and (c).

FIGURE 2.65

Three different types of MOSFETs introduced by ITRS roadmap.

2.31  Short-Channel Effects of MOSFET

A MOSFET device is considered to be short when the channel length is of the same order of magnitude as the depletion-layer widths (xdD, xdS) of the source and the drain junctions. Short-channel effects occur as the channel length L is reduced to increase both the operation speed and the number of components per chip.

The short-channel effects are attributed to two physical phenomena:

1.The limitation imposed on electron drift characteristics in the channel

2.The modification of the threshold voltage due to the shortening of the channel length

Reduction of channel length of MOSFETs leads to the short-channel effects such as:

•Reduction in the threshold voltage

•Drain-induced barrier lowering

•Increase in the saturation drain current with increasing VDS

•Increase in the off-state leakage current

•Punch-through effect

•Mobility degradation

•Increase in the parasitic resistance and the capacitance

•Hot carrier effect

All these effects are discussed in detail in the following sections.

2.32  Reduction of the Effective Threshold Voltage

In a long-channel device, channel formation is controlled by the gate and the substrate. The gate voltage controls all the space charge induced in the channel region. As the channel length decreases, the charge in the channel region decreases. As the drain bias is increased, the reverse biased space charge region at the drain extends farther into the channel and the gate control decreases (i.e., in a short-channel device the n+ type source and the drain induce a large amount of the depletion charge which cannot be neglected). For short-channel devices, the charge control of the channel is shared by the four terminals (gate, substrate, source, and drain), called charge sharing. The