Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

FIGURE 2.47

(a) ID versus VDS characteristics for an n-channel deletion mode MOSFET. (b) Symbol of an n-channel deletion mode MOSFET.

ID

Enhancement mode

Depletion mode

VGS

FIGURE 2.48

ID–VGS characteristics for depletion mode and enhancement mode MOSFETs.

2.19  Transconductance (gm)

Since a MOSFET operating in saturation region produces a current in response to its gate-source overdrive voltage, we define a figure of merit that indicates how well a device converts a voltage to a current. In processing signals we deal with the changes in voltages and currents, so here we define a figure of merit as the change in the drain current divided by the changes in the gate-source voltage, called the transconductance, denoted by gm, expressed as

p-substrate

δL

L

FIGURE 2.50

Reduction of channel length at saturation.

saturation voltage so that VDS > VDSSat, an even larger portion of the channel becomes pinched off. The effective channel length (i.e., the length of the

inversion layer) is reduced to L − L, where L is the length of the channel region where inversion charge is equal to zero as in Figure 2.50. The pinchoff point moves from drain end to the source end caused by increasing drain- to-source voltage. The electrons traveling from the source toward the drain traverse the inverted channel section of length L and then are injected into the depletion region of length L − L′ = L which separates the pinch-off point from the drain end.

The voltage remains constant at VGS − VTH = VDSsat, and the additional bias applied to the drain appears as a voltage drop across the narrow depletion

region between the channel end and the drain region. This voltage accelerates the electrons at the drain end of the channel and sweeps them across the depletion region into the drain. The channel length is reduced from L to L − L, a phenomenon known as channel-length modulation which is similar to base-width modulation in BJT. The shortening of the channel causes a larger current called channel-length modulation.

Channel-length modulation in a MOSFET is caused by the increase of the depletion layer width at the drain end with increased drain voltage. This leads to a shorter channel length and an increased drain current. An example of this is shown in Figure 2.51(a). The channel-length-modulation effect increases in small devices with low-doped substrates as in Figure 2.51(b).

Due to channel-length modulation, the effective channel length becomes L − L. The drain current in saturation can be written as

The above equation is the modified current equation of a MOSFET considering channel-length modulation.

The saturation current is not dependent on drain bias if one does not consider channel-length modulation (λ = 0). However, in reality the saturation mode current increases linearly with drain bias. The slope of this current– voltage curve in the saturation region is determined by the channel-length modulation parameter λ. Thus, in the saturation region the graph is not a straight line, and there is finite slope caused by channel-length modulation as in Figure 2.51(a).

The ID −VDS characteristics showing the effect of channel-length modulation are shown in Figure 2.52. The observed linear dependence of ID on VDS in the saturation region is represented in (2.131) by the factor (1 + λVDS). From Figure 2.52 it is seen that when the straight-line ID −VDS characteristics are extrapolated, they intercept the VDS axis at the point VDS = −VA, where VA

VGS2

ID

VGS1

VGS2 > VGS1

FIGURE 2.52

Effect of VDS on ID in the saturation region.

118 Technology Computer Aided Design: Simulation for VLSI MOSFET

is a positive voltage. Equation (2.131) indicates that ID = 0 at VDS = –1/λ. It follows that VA = 1/λ.

Therefore, VA is a process-technology parameter with the dimensions of V. For a given process, VA is proportional to the channel length L that the designer selects for a MOSFET. The voltage VA is referred to as the Early voltage.

Equation (2.131) shows that when channel-length modulation is taken into account, the saturation values of ID depend on VDS . Thus, for a given VGS, a change VDS causes a corresponding change ID in the drain current ID. The output resistance of the current source representing ID in saturation is no longer infinite. The output resistance ro is defined as

Thus the output resistance is inversely proportional to the drain current [39,40]. The output conductance gDS can be expressed as

λ is proportional to 1/L, and ID is proportional to 1/L:

Output conductance gDS is strongly dependent on channel length, and this strong dependence is expressed by

Unlike the Early effect in bipolar devices, the amount of channel-length modulation is under the circuit designer’s control. Because λ is inversely proportional to L, for a longer channel, the relative change in L for a given change in VDS is smaller. We may conclude that channel length modulation is more prominent in short-channel devices as shown in Figure 2.53.

FIGURE 2.53

Channel length modulation is more prominent for short-channel devices.

2.21  Substrate Bias Effects

The derivation of linear mode and saturation mode current-voltage characteristics is done based on the assumption that the substrate potential is equal to the source potential (i.e., VSB = 0). The threshold voltage is calculated without considering the substrate voltage. However, in many digital applications, the source potential can be larger than the substrate potential (i.e., VSB > 0). The influence of non-zero VSB must be accounted for by the threshold voltage VT. So the modified VT must be applied to the current characteristics. The threshold voltage is a function of the bulk-to-source voltage VBS through the substrate bias effect or backgate effect. The application of VBS (a negative voltage to avoid forward biasing the bulk-to source p-n junction) increases the depletion width, which increases the bulk charge as shown in Figure 2.54 and, thus, the threshold voltage. A solution to avoid the backgate effect is to make VBS = 0 by electrically shorting the source to the bulk as in Figure 2.55.

FIGURE 2.54

Variation of depletion charge with body effect.

Ideally, the source and drain regions should end at the edge of the gate oxide. In reality, both the source and the drain tend to extend somewhat below the oxide by an amount xd, called the lateral diffusion length. Hence, the effective channel of the transistor L becomes shorter than the length Ld (the length the transistor was originally designed for) by a factor L = 2xd. It also gives rise to a parasitic capacitance between the gate and the source (drain) that is called the overlap capacitance. This capacitance is strictly linear and has a fixed value:

Because xd is a technology-determined parameter, it is customary to combine it with the oxide capacitance to yield the overlap capacitance per unit transistor width Co .

2.23.2  Channel Capacitance

This is the most important MOS parasitic circuit element, the gate-to-channel capacitance CGC is divided into CGCS, CGCD, and CGCB (being the gate-to-source, gate-to-drain, and gate-to-body capacitances, respectively), depending upon the operation region and terminal voltages. This varying distribution is best explained with the simple diagrams of Figure 2.59. When the transistor is in cutoff as in Figure 2.59(a), no channel exists, and the total capacitance CGC appears between the gate and the body. In the resistive region as in Figure 2.59(b), an inversion layer is created, which acts as a conductor between the source and the drain. Consequently, CGCB = 0 as the body electrode is shielded from the gate by the channel. From symmetry, the capacitance distributes evenly between source and drain. Finally, in the saturation mode as in Figure 2.59(c), the channel is pinched off. The capacitance between gate and drain is approximately zero, and so is the gate-body capacitance. Hence, all the capacitances are between the gate and the source.

The actual value of the total gate-channel capacitance and its distribution over the three components is best explained with the help of a number of charts. The plot in Figure 2.60(a) shows the evolution of the capacitance as a

FIGURE 2.59

The gate-to-channel capacitance and their distribution over the other three terminals depending upon the operation region.