Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

statement “contact name=gate n.poly” because the workfunction of n+ polysilicon equals 4.17 eV.

The fabrication process, no matter how well controlled, introduces interface states at the SiO2-Si interface, which critically affects the electrical characteristics of the device. Interface states, whether inherent, process related, or operationally generated, were found to cause degradation in device parameters such as transconductance, carrier mobility, and threshold voltage and to generally reduce device reliability and lifetime [36,37]. The “interface” statement is used to define the interface charge density interfaces between semiconductors and insulators. It indicates that all interfaces between semiconductors and oxide have a fixed charge of 3 × 1010 C/cm2 [37].

contact name=gate n.poly interface qf=3e10

contact name=source neutral contact name=drain neutral contact name=substrate neutral

Step 6: Define doping in the MOSFET structure.

The next action, doping, is one of the most important actions a designer does to affect the electrical properties of the structure being designed. Silvaco allows the designer to specify the type of dopant and the concentration. It also allows the designer to specify the distribution of the doping material. ATLAS has the ability to distribute the dopants in a uniform, analytical Gaussian, or other supported profiles. For this device, all the doping will be defined in region 2, where the silicon is located. Initially a p-type uniformly distributed doping is specified in the whole region 2. It is followed by a Gaussian distribution n-type doping specification targeting the source and the drain region of the structure. The concentration listed in the command for Gaussian doping in the source and the drain will have the peak concentration = 1 × 1020 cm–3 at y = 0 and the characteristics = 0.05 which is the principal characteristic length of the implant (standard deviation) for which the doping level will drop off in a vertical direction. The lateral fall-off outside the x-coordinates mentioned in the doping statement is defined by the lat.char parameter.

#p-type doping with a uniform concentration throughout all of the silicon doping uniform conc=2e17 p.type direction=y regions=2

#Gaussain doping profile in the source

doping gaussian characteristic =.05 conc=1e20 n.type x.left=0 x.right=$gmin y.top=0 lat.char=0.05 direction=y

# Gaussain doping profile in the drain

doping gaussian characteristic =.05 conc=1e20 n.type x.left=$gmax x.right=3 y.top=0 lat.char =.05 direction=y

Step 7: Save and display the structure file.

The “master” after the name of the out file specifies that the output file needs to be written as a standard structure file instead of binary format. The generated MOSFET structure can be visualized with the help of TonyPlot.

struct outf=SOI.str master tonyplot SOI.str

Step 8: Select the models used in this simulation.

In this simulation, for mobility standard concentration dependent (conmob) and parallel field dependent mobility (fldmob) to model, the velocity saturation effect is chosen. For carrier statistics, Fermi-Dirac and band-gap narrowing (bgn) are chosen. The parameters evsatmod and hvsatmod with b.electrons and b.holes supplied are used to select a particular field-dependent equation to be used. Carrier generation and recombination are the processes by which the semiconductor material is moved away from thermal equilibrium and returned to equilibrium after being disturbed from it. For recombination Shockley-Read-Hall (SRH) and Auger recombination models are chosen.

In the presence of heavy doping (greater than 1018cm–3), the p-n product in silicon becomes doping dependent [38]. As doping increases, the band gap decreases, where the conduction band decreases the same amount as the valence band is raised. This feature is considered by using the model “BGN” (band-gap narrowing).

# model specification

models auger srh conmob fldmob b.electrons=2 b.holes=1 evsatmod=0 hvsatmod=0 bgn temperature=300

Step 9: Define the numerical methods.

The Newton method is chosen with a maximum number of iteration equal to 25. To overcome the problem with diverging solution with a poor initial guess, a “trap” statement is used, where maxtrap is the maximum allowed number of trials (default = 4) with the bias step reduced by the factor supplied in the parameter known as atrap. To enhance the performance for slow convergence, a variant of Newton’s method known as the Newton-Richardson method is enabled by the autonr parameter.

# method specification

method newton itlimit=25 trap atrap=0.5 maxtrap=4 autonr

FIGURE 5.10

Cross-sectional diagram of a fully depleted n-channel SOI MOSFET.

Step 11: Display the output characteristics.

# plot of the log files overlaid together

tonyplot -overlay SOI11.log SOI21.log SOI31.log SOI41.log

# denotes end of the program quit

5.12.2 Simulation Results

Figure 5.11 shows the simulated Id-Vds characteristics for the n-channel fully depleted SOI MOSFET device structure displayed in Figure 5.10 for gate bias 1.0, 1.5, 2.0, and 2.5 V, respectively.

5.13  Example 3: 0.18 µm Bulk nMOS

Transistor with Halo Implant

The device used for this simulation is a LDD 0.18 µm [39] n-channel MOSFET. The device is fabricated using silicon with a <100> orientation. The p-type substrate is formed by doping with 3 × 1013 atoms/cm3 of boron. The n– region is formed by implanting a dose of 1015 atoms/cm3, and the n+ region is formed by implanting 5 × 1015 atoms/cm3 of arsenic. The program starts with a mesh definition. The mesh is defined for one-half of the symmetric MOSFET structure. After all the process fabrication steps, the structure will be mirrored

FIGURE 5.11

Plot of drain current Ids as a function of drain-to-source voltage Vds for gate-to-source voltage Vgs = 1.0 V, 1.5 V, 2.0 V, and 2.5 V, respectively, obtained by simulation for an n-channel fully depleted SOI MOSFET.

to generate full MOSFET structure. The different steps performed to simulate the fabrication of n-channel MOSFET followed by extraction of different MOSFET parameters of it are described below. The status of the MOSFET structure and the effect of every successive process step can be visualized by inserting a command for plotting the structure (tonyplot structure_name. str) after every step described below.

5.13.1  Program for 0.18 µm Bulk nMOS

Step 1: Provide mesh definition and structure declaration.

#start process simulator ATHENA go Athena

#Define mesh for x-plane

line x loc=0.15 spac=0.1 line x loc=0.2 spac=0.006 line x loc=0.4 spac=0.006 line x loc=0.6 spac=0.01

# Define mesh for y-plane line y loc=0.0 spac=0.002 line y loc=0.2 spac=0.005

line y loc=0.5 spac=0.05 line y loc=0.8 spac=0.15

# structure declaration struct outfile=nmos_bulk.str

Step 2: Initialize silicon substrate of crystal orientation 100 with 1.0 × 1015/cm3 boron dopant added. A space multiplier (Space.mult = 2) is used to speed up the process. Decrease the space multiplier parameter to obtain a denser mesh with more accuracy.

init orientation=100 c.boron=1.0e15 space.mul=2

Step 3: Grow a smooth thin layer of SiO2 of depth 10 to 15 nm on the substrate to reduce the channeling effect and to prevent contamination of the substrate. The simplest deposit method in ATHENA is conformal deposition. It is used when the exact shape of the deposited layer is not critical. Dry oxidation is performed for 30 minutes at 1000°C. Then etch to obtain a uniform blanket of oxide of 0.02 µm thick.

diffus time=30 temp=1000 dryo2 press=1.00 hcl=3 etch oxide thick=0.02

Step 4: Use the default dual Pearson model to choose a boron implant with a dose of 8.0 × 1012 ions/cm2 with energy 100 keV. An n-channel MOS transistor must be developed on p-type silicon as this material under the gate must be inverted. Therefore, the next step is implantation of boron to create a p-well in the substrate. The nMOS fabrication could have started with an initial p-type substrate, but p-well implantation reviewed here is common in industry. ATHENA offers three different models for ion implantation [40]: (1) dual Pearson (default), (2) single Pearson, and (3) Monte Carlo.

implant boron dose=3.0e13 energy=200 pearson

Step 5: Move and settle the boron atoms. As a result of the ion implantation step, the net doping peaks at an average penetration depth with a specific doping concentration. In order to enhance the doping uniformity, the substrate is heated to high temperatures so that the boron atoms are given enough energy to move and settle more uniformly in the substrate. As a result of this heating in the presence of oxygen, an oxide is formed. Wet oxidation is used.

diffus temp=950 time=100 weto2 hcl=3

Step 6: Further propel the p-well into the substrate and increase the doping uniformity by performing more diffusion steps with varying temperatures, temperature change rates, and processing environments known as welldrive.

diffus time=50 temp=1000 t.rate=4.000 dryo2 press=0.10 hcl=3 diffus time=220 temp=1200 nitro press=1

diffus time=90 temp=1200 t.rate=-4.444 nitro press=1

Step 7: Etch all present oxide layers in order to obtain a surface on which to begin the process of defining physical MOSFET parameters.

etch oxide all

Step 8: Perform sacrificial cleaning in order to ensure that the surface is free from damage due to previous fabrication steps. In this process, a thin layer of silicon is sacrificed by first oxidation and then removal of the oxide produced.

diffus time=20 temp=1000 dryo2 press=1 hcl=3 etch oxide all

Step 9: Perform deposition of gate oxide by dry oxidation, with the thickness of the gate oxide playing a major role in determining the MOSFET characteristics that can be altered by controlling time and temperature.

diffus time=3 temp=895 dryo2 press=1.00 hcl=1

Step 10: Define the threshold voltage by implanting boron through the gate oxide. A higher dose of boron implant will lead to higher threshold voltage because it will be more difficult to invert the p-channel.

implant boron dose=1.5e13 energy=45 pearson

Step 11: Use conformal deposition of polysilicon to create the gate.

depo poly thick=0.2 divi=10

Step 12: Begin patterning of the polysilicon gate by etching 0.35 µm from the left side.

etch poly left p1.x=0.51

Step 13: Perform implantation through the deposited gate oxide layer t from the light drain/source.