Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

resistance value falls. However, for strong inversion, the increase of drain current with the increase of drain bias due to the above effects is counterbalanced somewhat due to better gate control at high gate bias. Therefore, the resultant rate of increase of drain current is small. Consequently, the output resistance remains nearly constant.

7.5  Hot Carrier Effects Due to Impact Ionization

If the drain voltage (and hence the lateral electric field ξy) is sufficiently high, the carrier velocity near the drain saturates. The length of the high field region is a function of channel length, oxide thickness, and gate and drain bias. Even by considering the scaling of supply voltage, the electric field in the high field region is strong enough (104 V/cm). Consequently, the electrons gain enough energy and collide with the bound electrons in the valence band to create impact ionization of silicon lattice atoms in scaled MOS transistors. These highly energetic electrons are referred to as hot electrons because if their kinetic energy is expressed as kTe, then Te becomes as high as 1000 K, which is much higher than the lattice temperature. As a result of the impact ionization process, electron-hole pairs are generated. Among these pairs, the electrons are collected by the drain which increases the drain current. On the other hand, the holes are pushed toward the source, which in turn are directed toward the substrate due to the action of the vertical electric field. This results in an impact ionization induced substrate current as illustrated schematically in Figure 7.29.

Depletion layer boundary

Substrate current

B

FIGURE 7.29

Substrate current due to impact ionization.

7.6  Characterization of Gate Dielectric

The thickness of the gate dielectric (SiO2 is the preferred gate insulator in the semiconductor industry because of the excellent compatibility of SiO2 with silicon and established performance record) is reduced from 300 nm for the 10 µm technology to 1.2 nm for the 65 nm technology. Scaling down of SiO2 thickness is essential for two reasons. First, with the scaling down of the oxide thickness, the gate capacitance Cox increases. This increases the transistor ON-current which leads to an increase of the circuit speed. The second reason is short channel effect immunity, as discussed earlier.

However, if the oxide becomes too thin, the electric field in the oxide becomes so high that it may cause dielectric breakdown. For oxide thickness less than 1.5 nm, tunneling leakage current becomes the most serious limiting factor that prevents the use of such thin film. The reduction of gate oxide thickness (has reached only a few atomic layers) results in an increase in field across the oxide. The high electric field leads to tunneling of electrons from the strongly inverted surface to gate and also from gate to the inverted surface through the gate oxide, resulting in gate oxide tunneling. When the electrons tunnel into the conduction band of the oxide layer, the resulting tunneling is referred to as Fowler-Nordheim tunneling [5]. On the other hand, if the electrons tunnel directly through the forbidden energy gap of the SiO2 layer, the resulting tunneling is referred to as direct tunneling.

In order to avoid the tunneling problem, there is an intense search of alternative dielectrics with high-κ (permittivity) which has properties very close to SiO2 but offers the opportunity to use a higher thickness for the gate insulator. The gate capacitance of a MOS transistor using an arbitrary dielectric material with thickness Td is given by

In (7.92), ε0 is the permittivity of free space, κd is the relative permittivity of dielectric material, A is the area of the conducting plates, and Td is the gate dielectric thickness. The thickness of the high-κ dielectric insulator is derived from the relation

HfO2 has a relative permittivity (κ) of ~24, six times larger than that of SiO2(κSiO2 ~ 3.9). Therefore, a 6-nm HfO2 film has effective oxide thickness (EOT) of 1 nm, in the sense both films produce the same oxide capacitance. However, the HfO2 film is physically much thicker compared to SiO2 film. Therefore the leakage current in the HfO2 film is several orders of magnitude

smaller than that through SiO2. Some other popular high-κ dielectric insulator materials are ZrO2 and Al2O3. However, the uses of high-κ dielectric insulator materials pose several problems in IC manufacturing. These include chemical reactions between these materials and the silicon substrate, lower surface mobility, and more oxide trapped charges. In order to reduce these problems to some extent, a thin SiO2 interfacial layer is inserted between the silicon substrate and the high-κ dielectric insulator.

In SPICE simulation, high-κ gate dielectric can be modeled as SiO2 with an equivalent oxide thickness. Alternatively, the value of the gate dielectric constant parameter (EPSROX) can be specified.

7.7 Capacitance Characterization

A VLSI circuit operates both under DC conditions (when the terminal voltages do not change with time) and time-varying conditions. The time-varying operation of the circuit is largely influenced by the various capacitors present in a MOS transistor. Therefore, proper characterization of the various capacitances of a MOS transistor is an essential task for IC designers. The capacitance model is based on the quasi-static approximation, which implies that the potential and charge density at any given point in the channel of the transistor follow the time-varying terminal voltages immediately without any delay. In other words, under quasi-static approximation, it is assumed that the time-varying terminal voltages do not change appreciably within the “transit time” duration of the device. The various intrinsic and extrinsic capacitors present within a MOS transistor are identified in the following sub-section.

7.7.1  Capacitance Components in a MOS Transistor

The various capacitors present within an n-channel MOS transistor are identified in Figure 7.30. For characterizing the various capacitances, the MOS transistor capacitors are divided into two types: intrinsic and extrinsic. The intrinsic region is identified as the region between the metallurgical source and the drain junction where the gate to S/D region is at flat band voltage. The capacitances involved within the intrinsic region are referred to as the intrinsic capacitances. The extrinsic capacitances that are basically the parasitic capacitances are further divided into five components: (1) the outer fringing capacitances between the poly-silicon gate and the S/D region: CFO; (2) the inner fringing capacitances between the poly-silicon gate and the S/D region: CFI; (3) the overlap capacitances between the gate and the heavily doped S/D

regions (as well as the bulk region), CGSO, CGDO (CGBO); (4) the overlap capacitances between the gate and the lightly doped S/D regions CGSOL, CGDOL; and (5) the source/drain junction capacitances CJS and CJD. The intrinsic capacitances

B

FIGURE 7.30

Identification of intrinsic and extrinsic capacitors present in an n-channel MOS transistor.

are shown bold in Figure 7.29. These are gate-to-source capacitance CGSI, gate- to-bulk capacitance CGBI, and gate-to-drain capacitance CGDI.

7.7.2  Characterization of Intrinsic Capacitances (Meyer’s Approach)

The simplest approach for characterizing the gate capacitances was developed by Meyer [15,16]. The simplified intrinsic capacitance model treats the intrinsic MOS capacitances as three lumped capacitances, gate-to-source capacitance CGS, gate-to-drain capacitance CGD, and gate-to-bulk capacitance CGB. The gate capacitances are attributed entirely to the changes in the gate charge, which is written in the following compact formulation:

In (7.93), CGZ represents the capacitance between the gate and the terminal Z (S/D), while VGZ represents the corresponding voltage difference. It is also assumed that all capacitances are reciprocal (e.g., CGD = CDG). From charge neutrality condition, we have

Here Qinv is the inversion charge density, and QB is the bulk charge density. In strong inversion, the channel charge density along the channel is given by (7.26) which is repeated here for convenience: