Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

In order to ease the task of circuit designers for predicting the circuit performances with technology generation, predictive technology model (PTM) has been developed by Zhao and Cao [4] based on physical models and early stage silicon data. The PTM of bulk CMOS is successfully generated for 130 nm to 32 nm technology nodes, with effective channel length as low as 13 nm. These have been used in the present chapter for device characterization.

7.3  Threshold Voltage Characterization

Accurate characterization of threshold voltage is one of the most important requirements for precise description of transistor behavior and the effect of such behavior on circuit performances. It may be noted that all the commercially available compact models mentioned earlier accurately characterize this important quantity. Consequently, the SPICE simulation tool by using such models properly takes care of the effects of threshold voltages of the individual MOS transistors on the circuit performances. However, it is essential for the designers to properly understand the behavior of this quantity under varying bias conditions and geometry of the device, at least in general, in order to intuitively justify the SPICE simulated performances of the circuits.

7.3.1  Threshold Voltage Characterization for Long Channel MOS Transistor

Throughout this chapter, the discussion is centered on n-channel enhancement mode transistor. In general, the conclusion drawn for an n-channel MOS transistor equally holds true for p-channel MOS transistor, with reversal of polarity of the bias voltages. Historically the source terminal is the conventional voltage reference mostly due to the dominance of digital circuits where source is considered as the reference voltage terminal.

7.3.1.1  Uniform Channel Doping

The schematic diagram of a long channel MOS transistor with uniformly doped substrate is shown in Figure 7.2. The theoretical definition of threshold voltage is based on the strong inversion condition. The threshold voltage is defined as the gate voltage when the surface potential or band bending reaches 2ΦF and the silicon charge (the square root) is equal to the bulk depletion charge for that potential [5]. This definition is valid for long channel MOS transistors. Based on the threshold voltage value, the operating region of a MOS transistor is broadly divided into three parts: First, if the applied gate bias is greater than the threshold voltage (VGS > VT), the inversion charge density is larger than the substrate doping concentration and the

FIGURE 7.2

Cross-sectional view of n-channel MOSFET.

transistor operates in a strong inversion region. In this region, drift current is the dominant carrier transport mechanism. Second, if the applied gate bias is much smaller than the threshold voltage (VGS > VT), the inversion charge density is smaller than the substrate doping concentration and the transistor operates in a weak inversion or sub threshold region. In this region, the diffusion current is the dominant carrier transport mechanism. Last, if the applied gate bias is very close to the threshold voltage, the inversion charge density is close to the substrate doping concentration and the region of operation is called a moderate inversion region. In this region, both diffusion and drift currents are equally important.

The threshold voltage of a long and wide channel MOS transistor with uniform doping is given as [5]

In (7.1a) and (7.1b), VFB is the flat band voltage, ΦF = kTq ln( NnAi ) is the Fermi potential, NA is the uniform p-type substrate doping concentration, and Cox is the oxide capacitance per unit area. QB is the depletion charge per unit area. For NMOS transistor QB is negative, and for PMOS transistor QB is positive. With the application of substrate bias VBS (<0 for NMOS and >0 for PMOS), the bulk depletion charge region is widened and the threshold voltage is increased as given as [5]:

This can be alternatively written as follows:

Here the quantity VT0 is referred to as the zero substrate bias large geometry threshold voltage. The factor

is referred to as the body-effect parameter. The substrate sensitivity is defined as

In (7.4b), m is referred to as the body-effect coefficient, Wdm is the width of the depletion region, and Cdm is the depletion capacitance.

This model is derived based on the assumption that the transistor is of long channel length and width and the substrate doping concentration is uniform. However, in current VLSI MOS transistors, the channel is doped non-uniformly in both vertical and lateral directions. These are collectively referred to as channel engineering. In addition, the channel lengths are very short. Therefore, the basic model needs to be modified. The following sub-sections describe how the vertical and lateral channel non-uniform doping effects are incorporated in industry standard compact models.

7.3.1.2  Vertical Channel Engineering

In the process of making a VLSI MOS transistor, several ion implantation doping process steps are required to adjust the threshold voltage and to suppress the punch-through and hot-carrier effects. The regions underneath the interface are doped with various concentrations along the vertical directions. The schematic diagram of a VLSI MOS transistor using vertical channel engineering is shown in Figure 7.3(a).

A shallow implantation of channel dopants of the same type as substrate is designed to obtain the desired threshold voltage value, and another deep implantation of channel dopants of the same type as substrate is designed to suppress the punch-through and drain-induced barrier lowering (DIBL) effect. A typical high-to-low doping profile in the vertical direction and the corresponding step

7.3.1.3 Halo/Pocket Implantation

For suppression of short channel effects, local high doping concentration regions near the source and drain junction edges are generally employed. This is known as lateral channel engineering or halo/pocket implantation. With this type of channel engineering, the doping concentration in the channel along the channel length becomes non-uniform. The schematic diagram of a VLSI MOS transistor using lateral channel engineering is shown in Figure 7.4(a). The lateral non-uniform doping with higher doping

Body B

Position Along the Channel

(b)

FIGURE 7.4

(a) A MOS transistor illustrating lateral channel engineering. (b) Step doping profile approximating the variation of the channel concentration from source to drain side.

concentration near the source/drain regions results in an increase in the average doping concentration in the channel and in turn results in an increase in the threshold voltage. This is sometimes referred to as reverse short channel effect (RSCE), because it helps to compensate charge sharing effects from the source/drain fields [7].

The lateral non-uniform doping concentration is approximated by a step doping profile along the channel, as shown in Figure 7.4(b). The average channel doping is given by [7,8]

(7.6)

In (7.6), NP is the pocket concentration. LPE0 is a fitting parameter extracted, whose value is to be extracted from the measured data. With the introduction of lateral doping, the threshold voltage model in (7.5) is modified as follows [8]:

In (7.7) the following BSIM4 model parameters are identified:

•K1 and K2 model the effects of a non-uniform vertical channel doping profile on threshold voltage.

•LPE0 and LPEB model effects of non-uniform lateral channel doping profile on threshold voltage. LPEB models VT(VBS) dependence.

•At zero substrate bias, only the term LPE0 represents lateral non-unifor- mity, and as the channel length is reduced, due to the fourth term, the threshold voltage increases. This is significant for a short channel MOS transistor.

7.3.2  Threshold Voltage Characterization for Short Channel MOS Transistor

The threshold voltage of a long channel device is found to be independent of the channel length and the applied drain voltage. However, in short channel devices, it has been experimentally found that the threshold voltage of a MOS transistor decreases as the channel length is reduced or the drain bias is increased. This effect is known as the short channel effect [5,7]. In addition, the dependence of the threshold voltage on the body bias becomes weak as the channel length is reduced.

280 Technology Computer Aided Design: Simulation for VLSI MOSFET

This leads to a smaller value of threshold voltage in short channel transistors compared to long channel transistors. This approach of explaining short channel effect is referred to as the charge sharing approach [7].

The decrease in the threshold voltage due to the reduction of channel length and increase in the drain bias can be explained by considering the surface potential. As the channel length decreases and the drain bias increases, the potential barrier (p-type region) between the source and the drain for the carriers (electrons) is lowered. Hence, less gate voltage is required to bring the surface potential to 2ΦF .

In effect the threshold voltage is lowered. This is called DIBL [5,7]. The concept of DIBL is explained in Figure 7.5(b), illustrating the surface potential plots along the channel for three different (long and short channel) devices [5]. It is observed that with small channel length and high drain bias, the potential barrier between the source and the drain is the lowest.

The short channel effect in threshold voltage is incorporated in a BSIM4 compact model as follows [8]:

In (7.8), VT represents the reduction of threshold voltage due to short channel effect. A simple and accurate model, derived in [9] is

In (7.9a) and (7.9b), Vbi is built-in potential of the source/drain (S/D) junction. This is given by

In (7.10), NDEP is the channel concentration at the edge of the depletion boundary, and NSD is the source-drain doping concentration. In (7.9a), lt represents the characteristic length given as

7.3.3  Techniques for Threshold Voltage Extraction

This sub-section outlines three commonly used approaches for extraction of the threshold voltage value from the measured drain current versus gate voltage transfer characteristics. A good review of these techniques including the background theory and others is provided in [11].

7.3.3.1  Constant Current Method

In the constant current method, the threshold voltage is evaluated as the value of the gate voltage, corresponding to a given arbitrary constant drain current IDS and drain voltage VDS <100 mV. A typical value for this arbitrary constant drain current is (Wm/Lm ) × 10−7 A, where Wm and Lm are the mask channel width and length, respectively. Because of its simplicity, this is the most widely used method in industry. However, this method has a serious drawback of being totally dependent on the arbitrary chosen value of the drain current.

7.3.3.2  Extrapolation in the Linear Region Method

The extrapolation in the linear region method is another very popular method for extracting the threshold voltage from the measured transfer characteristics of a MOS transistor. Both the drain current and the linear transconductance are degraded significantly at high gate voltages because of the decrease of mobility with the increasing normal field. The technique consists of determining the gate voltage intercept (i.e., IDS = 0) of the linear extrapolation of the IDS −VGS curve at its maximum first derivative point (i.e., the point of maximum transconductance). This is referred to as the linearly extrapolated threshold voltage VON . VON is obtained by subtracting VDS/2 from the intercept. The main drawback of this method is that the maximum slope point is often slightly greater ( 2kT/q − 4kT/q) than the threshold voltage VT at ψs (inv) = 2ΦF due to mobility degradation effects and the presence of significant source and drain series parasitic resistances.

7.3.3.3  Second Derivative Method

In this method, the threshold voltage is determined as the gate voltage at which the derivative of the transconductance (dgm/dVGS = d2 ID/dVGS2 ) is maximum.

7.3.4  Simulation Results and Discussion

In this sub-section the discussion on characterization of threshold voltage for VLSI MOS transistors is reviewed through SPICE simulation results. In the subsequent discussion considerably long channel width is considered so as to avoid the narrow channel width effect on the threshold voltage.