Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

These two different models are incorporated in SPICE simulator by using suitable mobility selector flags. It may be noted that all the mobility degradation models discussed above include the effect of vertical electric field only. It is observed that the mobility in a strong inversion region is a function of the gate bias. In the subthreshold region, the variation of Qinv with VGS cannot be modeled accurately. Therefore, μs becomes constant in the subthreshold region.

7.4.4  Carrier Velocity Saturation Model

Carrier velocity is another important physical phenomenon that critically affects the I-V characteristics of a short channel VLSI MOS transistor. If the lateral electric field is small, the drift velocity of the carriers is given by

In (7.36), µs is the surface mobility and is independent of the lateral field ξy. However, as the lateral field ξy becomes high, the carrier velocity no longer follows (7.36). With the increase of the lateral field, the kinetic energy of the carrier increases. When the energy of the carrier exceeds the optical phonon energy, an optical phonon is generated by the carrier, and in this process the carrier loses its velocity significantly. Consequently, the kinetic energy and therefore the drift velocity of the carriers cannot exceed a certain value. This limiting velocity is called the saturation velocity. The vd-ξy relationship is illustrated in Figure 7.12. An accurate model for the drift velocity is given by [3]

Carrier Velocity (cm/s)

Lateral Field (×104 V/cm)

FIGURE 7.12

Carrier velocity saturation.

In (7.37), α = 2 for electrons and α = 1 for holes. ξsat is the critical electric field at which the carrier velocity becomes saturated and is linked with the satu-

ration drift velocity of the carrier as ξsat = 2vdsat/µs. For electrons, vdsat varies between ~6–10 × 104 m/s and that for holes between ~4–8 × 104 m/s. The model

presented in (7.37) fits experimental data well but suffers from the drawback that it is computationally difficult to be incorporated in any circuit simulation program. In BSIM, a piece-wise velocity-field relationship is thus suggested. This is as follows [6]:

This model is in accordance with the experimental data.

7.4.5  Basic MOSFET I-V Model

Substituting (7.26) in (7.24) and carrying out the simple integration, we get the following expression as the basic MOSFET I-V model:

The following observations are made from (7.39):

•The drain current is proportional to the channel width W, surface

electron mobility µns , lateral electric field VDS/L, and the average inversion charge density Cox (VGS −VT − mVDS/2) .

•When the applied drain bias is small, the term VDS2 /2 can be neglected so that the drain current is linearly proportional to

the drain bias VDS , which means that the transistor is acting as a resistor.

•As the drain bias increases, the average inversion charge density

decreases and dIDS decreases. By differentiating (7.39) w.r.t VDS and

dVDS

putting equal to 0, we get

•The drain current that flows when the drain bias is saturated is referred to as the drain source saturation current. This is given as

inversion charge disappears at the drain side. This phenomenon is referred to as pinch-off. After the pinch-off region in the channel, there exists a depletion region. The electrons after reaching the pinch-off region are swept down by the drain bias and thus constant current flows, which is given by (7.41).

•Equations (7.39) and (7.41) form the basic I-V model for a long channel MOS transistor. Because of its simplicity, these equations are widely used by the designers for hand calculations. In addition, these are used in first-generation SPICE models [3].

•The transconductance parameter is defined as

It is observed that when a MOS transistor operates in the strong inversion region, the transconductance is proportional to the square root of the drain current.

7.4.6  MOSFET I-V Model with Velocity Saturation

Assuming the inversion charge density to be given by (7.26), the drain current from (7.24) is

In (7.43), the velocity saturation effect given by (7.38) has been assumed and ξy = dVdyCS . Performing the simple integration, we arrive at the following model for the I-V characteristics:

Thus the effect of velocity saturation is to reduce the long channel drain cur-

rent by the factor 1 + ξVsatDSL . When VDS is small or L is large, this factor reduces to 1 (i.e., velocity saturation becomes negligible). The drain current model in

(7.44) is valid before the carrier velocity saturates (i.e., in the linear or triode region).

If the drain voltage (and hence the lateral electric field ξy) is sufficiently high, the carrier velocity near the drain saturates. At this stage, the channel may be considered to be split into two portions: one adjacent to the source where the carrier velocity is field dependent, and the other near the drain where the carrier velocity is saturated to vdsat. At the junction between these

two portions, the channel voltage is VDSsat , and the lateral electric field is ξsat. Therefore, the saturation drain current is given as

Comparing (7.46) with (7.44), we arrive at the following expression for saturation drain voltage:

The following observations are made from (7.46) and (7.47):

• When the channel length is large or the gate overdrive voltage

(VGS −VT ) is low, ξsatL >> (VGS − VT ), VDSsat ≈ (VGS − VT )/m, we arrive at (7.40) (i.e., the long channel saturation drain voltage).

•For the very short channel transistor, ξsatL << (VGS − VT ) , VDSsat ≈ ξsatL the drain current becomes

•Thus, IDSsat is linearly proportional to (VGS −VT ), instead of the long channel quadratic dependence. In addition, IDSsat is proportional to W but less sensitive to L.

•The classical long channel model suggests that drain current saturates when the inversion charge density becomes zero, a phenomenon referred to as pinch-off. However, a more accurate description of the cause of drain current saturation is that the carrier velocity reaches

its maximum value vdsat at the drain. Thus instead of the pinch-off region, there is a velocity saturation region next to the drain where

the inversion charge density given as Qinv = Cox (VGS − VT − mVDSsat ) does not vanish.

•In order to increase IDSsat, there must be an increase in Cox (VGS −VT ).

This is achieved by reducing tox, minimizing VT, and increasing VGS. The limit of tox is determined by oxide tunneling leakage and reliability. On the other hand, the lower limit of VT is determined by the leakage current in the OFF state. The maximum value of VGS is the supply voltage VDD, which is determined by concerns over power consumption and reliability.

•It may be noted that for low power analog circuit operations, gate

overdrive voltage (VGS −VT ) is often taken to be nearly 0.1 V and assuming ξsat = 6 × 104 V/cm and L = 50 nm, ξsatL > (VGS − VT ), so that the transistor exhibits some long channel characteristics and consequently the long channel model may be used.

7.4.7  Parasitic Source Drain Resistance

It follows from (7.17) that for short channel effect immunity, the source/ drain junction depth must be reduced. Therefore, as shown in Figure 7.13, extra processing steps are performed to produce the shallow S/D junction extension between the deep junction and the channel. To further minimize dopant diffusion, the doping concentration in the shallow S/D extension

FIGURE 7.13

Source/drain series resistance in the SDE region.

is kept much lower compared to that in the deep S/D region. The shallow S/D extension along with light doping leads to parasitic S/D resistance. This is shown in Figure 7.13. The parasitic source and drain resistances are important device parameters that critically affect the MOS transistor performances. The drain current in the linear region with high gate bias is severely degraded due to this resistance, because channel resistance is lowest under such a bias condition. This is modeled in the presence of this resistance as follows:

In (7.49), IDS0 is the intrinsic current expression given by (7.44). RS is the parasitic source resistance. It appears from (7.49) that the effect of the series resistance is lowest in the saturation region, where VDS is high. A second effect of this resistance is the increase of VDSsat, as follows:

In (7.50), RS and RD are the parasitic source and drain resistances, respectively. Reducing the value of these resistances is thus an important task for both circuit and device designers. A popular option is to cover the drain and source regions with a low resistivity material such as titanium or tungsten. This process is called silicidation and it effectively reduces the sheet resistance of the S/D regions by a factor of 10. Another option to be used by the circuit designer is to make the transistor wide. With a process that includes silicida-

tion and proper attention to layout, parasitic resistance may be reduced.

7.4.8 Output Resistance

A typical I-V curve and its output resistance are shown in Figure 7.14. The drain current in the output I-V curve is divided into two parts: (1) the linear region, in which the drain current increases with the drain voltage, and (2) the saturation region, in which the drain current weakly depends upon the drain voltage. However, the output resistance curve reveals more detailed information about the various physical mechanisms involved in the saturation region. The output resistance is the reciprocal of the derivative of the I-V curve, and it is shown in Figure 7.14. The physical causes of such variation of the output resistance are the influences of drain voltage on the threshold voltage and a phenomenon called channel length modulation. The output resistance is divided into four regions.

The first region is the linear or triode region. In this region, the output resistance is very small because of the strong dependence of drain current on drain voltage. The other three regions belong to the saturation region,

It is instructive for IC designers to use the following set of equations for all sorts of hand analysis works.

V = ξsatL(VGS − VT )

DSsat mξsatL + (VGS − VT )

(7.54)

The parameters VT and VA are to be extracted from measurements. For simplicity, the value of the body-effect coefficient m may be considered to be unity.

7.4.9  Subthreshold I-V Model

When the applied gate voltage is smaller than the threshold voltage VT, ideally the drain current is zero. However, this does not happen in real devices and the drain current remains at a non-negligible level for several tenths of a volt below VT. This occurs because the inversion charge density does not drop to zero abruptly. Subthreshold characteristics are significant in scaled CMOS digital applications, because they describe how a transistor switches OFF. Thus, the subthreshold region, immediately below VT, in which ΦF < ψs < 2ΦF is referred to as the weak inversion region. Contrary to the strong inversion region, in which the drift current dominates, subthreshold conduction is dominated by the diffusion current, arising due to a gradient in minority carrier concentration. In weak inversion, an n-channel MOS transistor operates as an n-p-n bipolar transistor, where the source acts as the emitter, the substrate as the base, and the drain as the collector.

The inversion charge density is repeated here from (7.28)

In order to derive a relationship between ψs and VGS, the following expansion is made [12]: