Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

8.1  Introduction

The objective of this chapter is to fabricate a 5 μm 2D n-MOSFET (n-type metal-oxide-semiconductor field-effect transistor) using process simulator TSUPREM-4 [1] and device simulator Medici [2]. SUPREM is the acronym of Stanford University Process Engineering Modeling. Taurus TSUPREM-4 is for the version IV, which is a 2D simulation program. TSUPREM-4 is a computer program for the simulation of the fabrication steps required for the manufacture of silicon integrated circuits and for other integrated circuits (ICs). TSUPREM-4 simulates the changes in semiconductor structure which take place after various processing steps used during the actual fabrication procedure.

As the device dimensions have been reduced to micro or nano level, the specialization and application of technology computer aided design (TCAD) tools in new device creation for future technology generations are indispensable to harness the ever-increasing complexity and challenges of the “ever-shrinking transistors.” One of the main advantages of TCAD tools is visualization. For deep sub-micron devices, it is possible to visualize the evolution of the actual cross-sections of the structure during various process simulation steps in order to obtain better insight into the IC processing steps. TSUPREM-4, a popular commercial TCAD process simulator tool, allows verifying the entire structure after every realistic silicon wafer processing step via hands-on simulation, without the need for high-cost IC processing facilities. Moreover, these TCAD tools after calibration exhibit impressive predictive power with required accuracy, which can be utilized to speed up the technology integration and transfer to volume manufacturing. Therefore it is possible to experiment and explore the impact of process flow modifications at virtually no cost. This results in the possibility of manufacturing high-yield profitable product with short product development life cycles, which is absolutely necessary given the huge costs of nanoscale integrated circuit fabrication lines.

8.2  Why Silicon?

•Silicon can be easily oxidized to form high-quality silicon-dioxide

(SiO2) insulator, which is used as a masking or barrier material for selective doping steps required for IC fabrication.

•The SiO2 layer is essential in metal-oxide-semiconductor (MOS) device structure, and high-quality Si-SiO2 interface formation is possible to form the gate of MOSFET.

•Silicon also has wider band-gap than germanium, which means that silicon devices can operate at higher temperatures than their germanium counterparts.

•Silicon is available abundantly in nature as its primary constituent is ordinary sand. So, silicon provides a very low cost source of semiconductor device or IC fabrication material.

Actual industrial device fabrication consists of several steps that have been followed in fabrication procedure. The process starts with initializing a <100> silicon wafer of 5 μm, and it requires proper meshing of the device.

During the selective doping procedure, several portions of the wafer need to be masked or covered during various steps of the fabrication. By convention, the extension .tl1 is used for the mask layout files used by TSUPREM-4. This mask file named ‘t.tl1’ has been used here as an input file for the entire device fabrication where nine different mask names have been assigned for different fabrication steps.

To run any program in TSUPREM-4, the linux environment is required and one has to type ‘TSUPREM4’ followed by the filename having .inp extension in the terminal. The file in which the script is written is named MOSFET. inp. To run this script file, the command would be ‘TSUPREM4 MOSFET.inp’. With this script file another file is essential to execute the program: the mask file. The mask file is of extension .tl1. Here the mask file name is t.tl1, which contains the name of the masks with their length. Mask file has to be linked with the MOSFET.inp file as an input file in the beginning of its script file by the command MASK IN.FILE = t.tl1. Now it is possible to call any of its mask names when required. Here masks used in the t.tl1 file are of names gateoxet, nbl, Nplus, contact, metal1, metal2, metal3, and gateunderdoping. All lengths are by default in micrometers. The first statement of the mask file 1e3 or 1000 signifies the length mentioned here divided by 1e3 to convert it into micrometers. For example, in the mask named gateoxet, only one length is mentioned here from (1600–4100); that is why ‘1’ is mentioned after the mask name, like gateoxet 1. (1600–4100) μm signifies that it is the length 1.6 to 4.1 μm of the 0 to 5 μm device as it is divided by 1e3. Similarly for mask name contact, there are three lengths, so 3 is mentioned after the mask name contact, like contact 3, and different lengths are (300–1100), (2550–2850), and (4400–4850).

8.5  Defining the Initial Mesh

SELECT TITLE=“Initial Mesh”

PLOT.2D GRID C.GRID=8

It is clear from Figure 8.1 that meshing density is very high on the top portion of the wafer as the device structure will be grown there, so carrier flow and any other changes due to the terminal voltages will take place there.

8.6  N-Buried Layer

An N-buried layer (NBL) is implanted on this wafer which allows source voltage to be raised above the substrate voltage and to avoid leakage current toward the base which could be avoided by silicon-on-insulator (SOI) type devices. SOI structures become very unstable in high voltages as a reversebiased drain-bulk p-n junction generates a huge amount of heat that cannot be dissipated with an insulator, and self heating becomes a serious concern in terms of device reliability issues [9–10]. Therefore, antimony of dose 1e15 cm–3 (which equals 1 × 1015 cm–3) has been implanted followed by drive in voltage to place the NBL layer at the proper position on the wafer. This N-layer in P-type wafer will create a p-n junction that will stop high bottom leakage current flow due to high supply voltage at the drain end. As both initial wafer and buried layer are doped by boron and antimony of dose 1e15 cm–3, respectively, a p-n junction of equal depletion depth in both sides will be formed. For the actual structure an epitaxial layer of 14 μm is grown on this wafer where device parameter optimization is possible due to this epitaxial layer.

8.7  Oxidation and Growth of the Initial Oxide

The step required for creating an oxide layer on a semiconductor is called oxidation. For oxidation of silicon, oxygen is made to react with silicon at 800 to 1200°C. For wet oxidation the presence of H2O in the reaction is essential. Though the dry oxidation rate is slow, the quality of oxide grown in this procedure is very good. Usually, dry oxidation is done in the presence of inert gas that acts as a carrier to control oxygen. Inert gas will also ensure that any other gas cannot take part in this reaction. In TSUPREM-4 the diffusion statement is used for this purpose. For fabrication of desired device structure, several steps may be used for the oxidation. The first line of the

statement of the program below signifies that the initial temperature of the furnace is 800°C which will rise and reach the final temperature 1000°C for 20 minutes. Similar steps will be followed by changing conditions.

This layer is basically grown on the wafer for masking purposes which is required for the dopant implementation for NBL layer formation. As there is no mask assigned on it before the diffusion step, the entire SiO2 layer will be formed on top of the whole wafer.

DIFFUSION TEMPERAT=800 T.FINAL=1000 TIME=20 F.O2=0.5 F.N2=9.5 DIFFUSION TEMPERAT=1000 TIME=65 F.O2=0.5 F.N2=9.5

DIFFUSION TEMPERAT=1000 TIME=5 F.O2=9.5

DIFFUSION TEMPERAT=1000 TIME=190 F.O2=5.975 F.H2=10.4 F.HCL=0.475 DIFFUSION TEMPERAT=1000 TIME=1 F.O2=5.5 F.N2=5

DIFFUSION TEMPERAT=1000 TIME=10 F.N2=10

DIFFUSION TEMPERAT=1000 T.FINAL=800 TIME=50 F.N2=10 print layers

8.8  Wafer Masking for Buried Layer Implantation

As the middle portion of wafer material has been chosen for the dopant implantation for NBL layer formation, so the rest of the wafer top needs to be covered by masking material, as a negative photoresist is being used here on the wafer of thickness 1 μm. The mask used here from the mask file (t.tl1) is nbl. It will be developed and be a selective part of the photoresist, and oxide will be etched out simultaneously due to the nature of the photoresist material and the etchant.

DEPOSIT PHOTORESIST NEGATIVE THICKNESS=1 EXPOSE MASK=nbl

DEVELOP etch oxide

The above sets of commands are used to display the device structure at any fabrication step as in Figure 8.2. These sets of commands can be used after every step of fabrication to have a look at the device structure formed at that point of time. Plot.2D will plot the characteristics, boundaries, junctions, and depletion edges of the two-dimensional simulated structure. The title of the paragraph will be printed along with the simulated output as mentioned here: “Deposition of negative photoresist.” Different colors have been assigned for different materials to display at the output. Different doping contour is being plotted by assigning different colors by FOREACH command. This procedure has been repeated for different dopants such as boron, phosphor,

8.9  Screen Oxidation

A layer of thin oxide is required to form on the wafer at the time of dopant implantation. This layer of oxide is called screen oxide and it protects the wafer when dopant bombardment takes place during the ion implantation procedure. Again, few oxidation steps are required in various controlled conditions.

DIFFUSION TEMPERAT=800 T.FINAL=900 TIME=10 F.O2=0.5 F.N2=9.5 DIFFUSION TEMPERAT=900 TIME=15 F.O2=0.5 F.N2=9.5

DIFFUSION TEMPERAT=900 TIME=5 F.O2=9.0

DIFFUSION TEMPERAT=900 TIME=5 F.O2=9.5

DIFFUSION TEMPERAT=900 TIME=28 F.O2=9.0 F.HCL=0.19 DIFFUSION TEMPERAT=900 TIME=5 F.O2=9.0

DIFFUSION TEMPERAT=900 TIME=30 F.N2=10.0

DIFFUSION TEMPERAT=900 T.FINAL=800 TIME=37.5 F.N2=10 print layers

8.10  Buried Layer Implantation

Due to nbl mask, which is defined as 2000 to 3000 in mask file, which effectively will be 2 to 3 μm as the rule defined in the mask file, there will be an opening of 2 to 3 μm on the wafer. The statement implant antimony will implant through it. As few other conditions like dopant angle of dopant implantation, dose and energy of implanted dopant by which it will be implanted into the wafer, and the tilt at which it will be implanted need to be