Книги+1 / 2013 [Chandan_Kumar_Sarkar]_Technology_CAD

7.4.10  Characterization of Poly-Silicon Gate Depletion Effect

The use of poly-silicon gates is considered as an advantage in modern CMOS technology. This is because the source and drain regions can be self-aligned to the gate, thus eliminating parasitic from overlay errors. The poly-silicon is usually heavily doped to behave almost similar to that of metal. However, in many process technologies, it is not possible to dope the poly-silicon gate to arbitrarily high concentrations. Therefore, a thin depletion layer is formed at the interface between the poly-silicon and the gate oxide, with the application of gate voltage.

7.4.10.1  Reduction of Gate-Source Voltage

Although the depletion region is very thin, its effect cannot be ignored in the deca-nanometer MOSFETs, because the gate oxide thickness is also very small. This is especially critical with the dual n+-p+ poly-silicon gate process in which the gates are doped by ion implantation. The effect of the presence of such a depletion region is that the voltage drop across the gate oxide and the substrate is reduced, because part of the gate voltage will be dropped across the depletion region in the gate. Consequently, the effective gate voltage is reduced.

Figure 7.15 shows an n-channel MOS transistor with a depletion region in the n+ poly-silicon gate. Let us assume that the doping concentration in the poly gate near the interface is Np, and the potential drop across the depletion region in the poly-silicon gate is ψp. From the depletion approximation, the depletion charge density in poly-silicon is

FIGURE 7.15

Poly gate depletion phenomenon.

304 Technology Computer Aided Design: Simulation for VLSI MOSFET

In (7.68), ψp is the potential drop across the poly-silicon gate, and γp is given by

While writing (7.71), it has been considered that the normal component of electrical displacement is continuous across the interface. From (7.70) and (7.71), the following quadratic equation can be derived:

Solving (7.72), and taking the positive root, the effective gate voltage is found to be

It is observed that if tox = 30A0, the effective gate voltage can be reduced by up to 10% due to the poly-silicon gate depletion effect. In a BSIM compact model, Np is denoted by NGATE and is considered as a model parameter.

7.4.10.2  Effect on Threshold Voltage

Let us now investigate the effect of poly-silicon gate depletion on the threshold voltage of a MOS transistor. The condition for charge balance is

When the gate is positively biased, the positive charge on the gate is supported by the depletion charge due to the donor ions at the poly-Si/SiO2 interface of an n+ poly-silicon gate. From (7.68),

Thus it is observed that due to the poly-silicon gate depletion effect, the threshold voltage is increased by an amount

7.4.10.3  Effect on Oxide Thickness

Because a depletion layer is present in the gate, it may be thought that a polysilicon gate capacitor is added in series with the oxide capacitor. The effect of this is that the oxide dielectric thickness is increased, such that the effective oxide thickness is

In (7.79), Wdp is the poly-silicon gate depletion width that is related to the potential drop in the depletion region through

7.4.10.4  Electrical Oxide Thickness

It may be noted in this connection that the charge sheet approximation considered in all calculations presented so far is not true in a fine sense. The assumption that the inversion layer is infinitely thin therefore needs rigorous consideration. To properly calculate the shape of the inversion region, Poisson’s equation has to be solved simultaneously with Schrödinger’s equation, which governs the behavior of tightly confined particles. The average location of the inversion charge below the Si-SiO2 interface is called the inversion layer thickness tinv. Then the effective (often called the electrical oxide thickness, in compact model terminology) that determines the capacitive coupling between the gate and the channel charge becomes

The solution to the poly-silicon depletion effect is to dope the poly-silicon heavily. However, very heavy doping may cause dopant penetration from the gate through the oxide into the substrate. Poly-silicon gate depletion effect is eliminated in advanced MOS technology by replacing the gate material with a pure metal. NMOS and PMOS transistors may require two different metals (with metal work functions close to those of n+ and p+ poly-silicon) in order to achieve the optimal threshold voltage [13].

7.4.11  Simulation Results and Discussion

7.4.11.1  Variation of Drain Current, Transconductance, and Output Resistance with Gate Voltage

The variations of drain current with applied gate bias and low drain bias for three different substrate biases are shown in Figure 7.16. It is observed from the figure when the gate bias is just above threshold voltage, the current increases at a faster rate, compared to high gate bias. This is because of the carrier mobility degradation phenomenon occurring at higher gate bias. This is also demonstrated through Figure 7.17, which shows the variation of the transconductance with applied gate bias for low drain bias. The same graphs plotted for high drain bias are shown in Figures 7.18 and 7.19, respectively. It is observed that with high drain bias, the mobility degradation phenomenon affecting the drain current is somewhat counterbalanced due to the high drift velocity of the carriers. The variation of output resistance with applied gate bias is shown in Figure 7.20. It is observed that when the transistor operates in the subthreshold region, the output resistance is very high. This is simple to explain by considering the fact that in the subthreshold region, a very small amount of drain current flows. On the other hand, in a strong inversion region, the output resistance drops and the value remains fairly constant with increase of gate bias.

and from simulation results, this is 24.41 V–1 at VBS = 0 V. The effect of substrate bias on the transconductance generation efficiency is also observed. As the substrate bias increases (i.e., as the substrate becomes more reverse biased), the depletion depth increases. Therefore, the depletion capacitance reduces and hence the subthreshold swing factor also reduces. Thus the ratio (gm/IDS ) increases.

The intrinsic voltage gain of a MOS transistor is defined as gmR0 , where R0 is the output resistance. The variation of output resistance and transconductance with applied gate bias is recalled in Figure 7.24(a). It is observed that at low VGS, when the transistor operates in weak inversion, the transconductance is low, but the output resistance is very high. The variation of the intrinsic gain with the applied gate bias is shown in Figure 7.24(b). Consequently, the intrinsic gain is high at the weak inversion region. As the gate bias is increased, so that the transistor starts to operate in the strong inversion region, the output resistance falls. Thus although the transconductance increases, the intrinsic gain falls. The effect of output resistance plays a significant role in determining the intrinsic gain of a MOS transistor.

Non-linearity of a device is manifested by the presence of higher-order harmonics at the output signal. The linearity of a MOS transistor is quantified in this work through the parameter VIP3. This is the extrapolated gate voltage amplitude, at which the third harmonics of the drain current become equal to the fundamental tone of the drain current [14]. This is mathematically defined as

VIP3 = 24 gm

|gm3|

Here

gm3 = ∂3 IDS

∂VGS3

The variation of gm3 with applied gate bias is shown in Figure 7.25(a). The VIP3 peak shown in Figure 7.25(b) is due to the second-order interaction effect and can be explained as a cancellation of the third non-linearity coefficient (i.e., gm3) (see Figure 7.25a) by device internal feedback around a second-order non-linearity [14]. It is observed that the linearity of the device is poor when it operates in a weak inversion region. Therefore, for better linearity performance, the device must work in a strong inversion region.